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Date:   Tue, 16 May 2023 11:14:52 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc:     Peter De Schrijver <pdeschrijver@nvidia.com>, jonathanh@nvidia.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, devicetree@vger.kernel.org,
        linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
        stefank@nvidia.com
Subject: Re: [PATCH v4 5/6] dt-bindings: Add support for tegra186-bpmp DRAM
 MRQ GSCs
Message-ID: <ZGNJjFOUFZ2rYu5X@orome>
References: <20230511132048.1122075-1-pdeschrijver@nvidia.com>
 <20230511132048.1122075-6-pdeschrijver@nvidia.com>
 <80ff83ab-d5e9-7a00-1099-a752330ef28d@linaro.org>
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On Fri, May 12, 2023 at 08:45:22AM +0200, Krzysztof Kozlowski wrote:
> On 11/05/2023 15:20, Peter De Schrijver wrote:
> > Add memory-region property to the tegra186-bpmp binding to support
> > DRAM MRQ GSCs.
>=20
> Use subject prefixes matching the subsystem (which you can get for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching).
>=20
> >=20
> > Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
> > Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > ---
> >  .../firmware/nvidia,tegra186-bpmp.yaml        | 37 +++++++++++++++++--
> >  1 file changed, 34 insertions(+), 3 deletions(-)
> >=20
> > diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186=
-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpm=
p.yaml
> > index 833c07f1685c..f3e02c9d090d 100644
> > --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.y=
aml
> > +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.y=
aml
> > @@ -57,8 +57,11 @@ description: |
> >    "#address-cells" or "#size-cells" property.
> > =20
> >    The shared memory area for the IPC TX and RX between CPU and BPMP are
> > -  predefined and work on top of sysram, which is an SRAM inside the
> > -  chip. See ".../sram/sram.yaml" for the bindings.
> > +  predefined and work on top of either sysram, which is an SRAM inside=
 the
> > +  chip, or in normal SDRAM.
> > +  See ".../sram/sram.yaml" for the bindings for the SRAM case.
> > +  See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for binding=
s for
> > +  the SDRAM case.
> > =20
> >  properties:
> >    compatible:
> > @@ -81,6 +84,11 @@ properties:
> >      minItems: 2
> >      maxItems: 2
> > =20
> > +  memory-region:
> > +    description: phandle to reserved memory region used for IPC between
> > +      CPU-NS and BPMP.
> > +    maxItems: 1
> > +
> >    "#clock-cells":
> >      const: 1
> > =20
> > @@ -115,10 +123,15 @@ properties:
> > =20
> >  additionalProperties: false
> > =20
> > +oneOf:
> > +  - required:
> > +      - memory-region
> > +  - required:
> > +      - shmem
> > +
> >  required:
> >    - compatible
> >    - mboxes
> > -  - shmem
> >    - "#clock-cells"
> >    - "#power-domain-cells"
> >    - "#reset-cells"
> > @@ -184,3 +197,21 @@ examples:
> >              #thermal-sensor-cells =3D <1>;
> >          };
> >      };
> > +
> > +  - |
> > +    #include <dt-bindings/mailbox/tegra186-hsp.h>
> > +
> > +    bpmp {
> > +        compatible =3D "nvidia,tegra186-bpmp";
> > +        interconnects =3D <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
> > +                        <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
> > +                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
> > +                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
> > +        interconnect-names =3D "read", "write", "dma-mem", "dma-write";
> > +        mboxes =3D <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB
> > +                            TEGRA_HSP_DB_MASTER_BPMP>;
> > +        memory-region =3D <&dram_cpu_bpmp_mail>;
>=20
> I am not sure if difference with one property justifies new example...

It makes sense in this case, in my opinion, because both memory-region
and shmem properties are mutually exclusive, so this is a good way to
make sure both validation paths are tested.

Thierry

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