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bh=Pf1n0pD+n5MYVam+kfSL7HSK5MrACb9JW8pF1eQ2LGo=; b=fDOKD3hpVxnw0IxL4IhPlY9JI7lHUOj+e7/SnkT3h0K4JbFJ+K7eII2IIfk/nqfp5E hCEHas0Pm4Z32EEy25INBUZZFqwRZHadE+6w6VBKGRZLezqW2NI7Y3RlilfsX1KV3Mk6 vjXi14qjCIX1muaPpvYo7Bi5DzTK4WBaCB5sIcrbKcWiYxEGHbXqiIUzUjQZ4mCwySWV zor3cxWfxAJiBw5QRvFVgxl73cbJDM8THtZ8pxEP572EmLJjTglTWFoDZPJKslyyj42s CESUIQECkstGVhELY2winhL9ovnAJ+72PhkCxhYoWh5yjr7BJCBqEOe74FUmedPuz0wQ jQ6g== X-Gm-Message-State: AC+VfDyvWsrGjRgDDzlE+lIC6iC+ySwc64Q3H+KihJU8866JmF8Byd1W b2wJWirkutaKPtPMNFAlJPQHRe7Adb92ZfMl94jPwA== X-Received: by 2002:a1f:e601:0:b0:44f:d211:2df3 with SMTP id d1-20020a1fe601000000b0044fd2112df3mr13694504vkh.13.1684231674434; Tue, 16 May 2023 03:07:54 -0700 (PDT) MIME-Version: 1.0 References: <20230417125844.400782-1-brgl@bgdev.pl> <20230417125844.400782-5-brgl@bgdev.pl> In-Reply-To: <20230417125844.400782-5-brgl@bgdev.pl> From: Bartosz Golaszewski Date: Tue, 16 May 2023 12:07:43 +0200 Message-ID: Subject: Re: [PATCH v4 4/5] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU To: Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon , Arnd Bergmann Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 17, 2023 at 2:58=E2=80=AFPM Bartosz Golaszewski = wrote: > > From: Bartosz Golaszewski > > The GPU SMMU will require the clocks property to be set so put the > relevant compatible into the adreno if-then block. > > Signed-off-by: Bartosz Golaszewski > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Docu= mentation/devicetree/bindings/iommu/arm,smmu.yaml > index ba677d401e24..53bed0160be8 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -79,6 +79,7 @@ properties: > - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "= arm,mmu-500" > items: > - enum: > + - qcom,sa8775p-smmu-500 > - qcom,sc7280-smmu-500 > - qcom,sm6115-smmu-500 > - qcom,sm6125-smmu-500 > @@ -331,7 +332,9 @@ allOf: > properties: > compatible: > contains: > - const: qcom,sc7280-smmu-500 > + enum: > + - qcom,sa8775p-smmu-500 > + - qcom,sc7280-smmu-500 > then: > properties: > clock-names: > @@ -413,7 +416,6 @@ allOf: > - nvidia,smmu-500 > - qcom,qcm2290-smmu-500 > - qcom,qdu1000-smmu-500 > - - qcom,sa8775p-smmu-500 > - qcom,sc7180-smmu-500 > - qcom,sc8180x-smmu-500 > - qcom,sc8280xp-smmu-500 > -- > 2.37.2 > Gentle ping for a review and a pick up. The DT patches that use this schema are in next now so check_dtbs will now fail. Bart