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Message-ID: <4a51d30f-7d20-b008-3d2f-1187fecbc4a5@monstr.eu>
Date:   Tue, 16 May 2023 13:09:27 +0200
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Subject: Re: [PATCH 18/23] arm64: zynqmp: Setup clock for DP and DPDMA
Content-Language: en-US
To:     Michal Simek <michal.simek@amd.com>, linux-kernel@vger.kernel.org,
        michal.simek@xilinx.com, git@xilinx.com
Cc:     Andrew Davis <afd@ti.com>,
        Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Tretter <m.tretter@pengutronix.de>,
        Parth Gajjar <parth.gajjar@amd.com>,
        Rob Herring <robh+dt@kernel.org>,
        Robert Hancock <robert.hancock@calian.com>,
        Vishal Sagar <vishal.sagar@amd.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
References: <cover.1683034376.git.michal.simek@amd.com>
 <807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com>
From:   Michal Simek <monstr@monstr.eu>
In-Reply-To: <807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com>
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Precedence: bulk


On 5/2/23 15:35, Michal Simek wrote:
> Clocks are coming from shared HW design where these frequencies should be
> aligned with PLL setup.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
>   arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi       | 4 ++++
>   arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 ++
>   arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 ++
>   3 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> index 681885c9bcbb..581221fdadf1 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> @@ -248,10 +248,14 @@ &xilinx_ams {
>   
>   &zynqmp_dpdma {
>   	clocks = <&zynqmp_clk DPDMA_REF>;
> +	assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
>   };
>   
>   &zynqmp_dpsub {
>   	clocks = <&zynqmp_clk TOPSW_LSBUS>,
>   		 <&zynqmp_clk DP_AUDIO_REF>,
>   		 <&zynqmp_clk DP_VIDEO_REF>;
> +	assigned-clocks = <&zynqmp_clk DP_STC_REF>,
> +			  <&zynqmp_clk DP_AUDIO_REF>,
> +			  <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */
>   };
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index 817d756142ab..4f18b3efcced 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -99,10 +99,12 @@ &zynqmp_dpsub {
>   	status = "disabled";
>   	phy-names = "dp-phy0", "dp-phy1";
>   	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
> +	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
>   };
>   
>   &zynqmp_dpdma {
>   	status = "okay";
> +	assigned-clock-rates = <600000000>;
>   };
>   
>   &usb0 {
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index e07cec231ee0..77bc806b15a1 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -80,10 +80,12 @@ &zynqmp_dpsub {
>   	status = "disabled";
>   	phy-names = "dp-phy0", "dp-phy1";
>   	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
> +	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
>   };
>   
>   &zynqmp_dpdma {
>   	status = "okay";
> +	assigned-clock-rates = <600000000>;
>   };
>   
>   &usb0 {

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs