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Date:   Tue, 16 May 2023 12:53:12 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Thierry Reding <thierry.reding@gmail.com>
CC:     Conor Dooley <conor@kernel.org>,
        Peter De Schrijver <pdeschrijver@nvidia.com>,
        <jonathanh@nvidia.com>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <stefank@nvidia.com>
Subject: Re: [PATCH v4 4/6] dt-bindings: Add support for DRAM MRQ GSCs
Message-ID: <20230516-cadet-enslave-208d91e66b32@wendy>
References: <20230511132048.1122075-1-pdeschrijver@nvidia.com>
 <20230511132048.1122075-5-pdeschrijver@nvidia.com>
 <20230511-carnivore-legend-17206803d713@spud>
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On Tue, May 16, 2023 at 11:12:50AM +0200, Thierry Reding wrote:
> I think Peter had to add these explicitly because the defaults are 2 and
> 1, respectively, and DTC was warning about this. I suppose the "reg"
> property could be adjusted to use the defaults, but on the other hand I
> find that it's good if the examples match reality and we need size-cells
> to be 2 on Tegra.

Huh, caught out by an abnormal example!
If it avoids an error & matches the use-case it seems like a good idea to
leave it as-is. Here's an unqualified
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
instead of the previous qualified one.

Thanks,
Conor.

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