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Message-ID: <bd074e2b-9739-a5ba-d076-94a3ac04d9b2@monstr.eu>
Date:   Tue, 16 May 2023 14:49:52 +0200
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Subject: Re: [PATCH 07/23] arm64: zynqmp: Add pmu interrupt-affinity
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To:     Michal Simek <michal.simek@amd.com>, linux-kernel@vger.kernel.org,
        michal.simek@xilinx.com, git@xilinx.com
Cc:     Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>,
        Harini Katakam <harini.katakam@amd.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
        Parth Gajjar <parth.gajjar@amd.com>,
        Piyush Mehta <piyush.mehta@xilinx.com>,
        Rob Herring <robh+dt@kernel.org>,
        Robert Hancock <robert.hancock@calian.com>,
        Tanmay Shah <tanmay.shah@amd.com>,
        Vishal Sagar <vishal.sagar@amd.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
References: <cover.1683034376.git.michal.simek@amd.com>
 <4c6674bf7e048e7370248e50ed3d011d604d020e.1683034376.git.michal.simek@amd.com>
 <4e5fc3ff-5b70-20a9-101a-cba9d20fc961@monstr.eu>
From:   Michal Simek <monstr@monstr.eu>
In-Reply-To: <4e5fc3ff-5b70-20a9-101a-cba9d20fc961@monstr.eu>
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On 5/16/23 13:05, Michal Simek wrote:
> 
> 
> On 5/2/23 15:35, Michal Simek wrote:
>> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>>
>> Explicitly specify interrupt affinity to avoid HW perfevents
>> need to guess. This avoids the following error upon linux boot:
>> armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
>> guessing.
>>
>> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>> ---
>>
>>   arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi 
>> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> index 61c7045eb992..a117294dc890 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> @@ -161,6 +161,10 @@ pmu {
>>                    <0 144 4>,
>>                    <0 145 4>,
>>                    <0 146 4>;
>> +        interrupt-affinity = <&cpu0>,
>> +                     <&cpu1>,
>> +                     <&cpu2>,
>> +                     <&cpu3>;
>>       };
>>       psci {
> 
> Applied.
> M

Actually remove this one from my queue because there were comment from Laurent.

M


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs