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Message-ID: <151169f7-dcdb-47f1-9616-67c3c388a233@linaro.org>
Date:   Tue, 16 May 2023 18:30:55 +0200
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Subject: Re: [PATCH] arm64: dts: microchip: add missing cache properties
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To:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Lars Povlsen <lars.povlsen@microchip.com>,
        Steen Hegelund <Steen.Hegelund@microchip.com>,
        Daniel Machon <daniel.machon@microchip.com>,
        UNGLinuxDriver@microchip.com, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
References: <20230421223155.115339-1-krzysztof.kozlowski@linaro.org>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20230421223155.115339-1-krzysztof.kozlowski@linaro.org>
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On 22/04/2023 00:31, Krzysztof Kozlowski wrote:
> As all level 2 and level 3 caches are unified, add required
> cache-unified and cache-level properties to fix warnings like:
> 
>   sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> ---

Anyone from Microchip picking this up?

Best regards,
Krzysztof