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References: <20230515210545.2100161-1-gnstark@sberdevices.ru>
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From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date:   Tue, 16 May 2023 21:08:26 +0200
Message-ID: <CAFBinCCc+t7Ks6fqz38cVrufPRFdxFgC9Qp+JhcM1KfD6pupTg@mail.gmail.com>
Subject: Re: [PATCH v1] meson saradc: fix clock divider mask length
To:     George Stark <gnstark@sberdevices.ru>
Cc:     jic23@kernel.org, lars@metafoo.de, neil.armstrong@linaro.org,
        khilman@baylibre.com, jbrunet@baylibre.com,
        andy.shevchenko@gmail.com, nuno.sa@analog.com,
        linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
        kernel@sberdevices.ru
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Hi George,

thank you for this patch!

On Mon, May 15, 2023 at 11:06=E2=80=AFPM George Stark <gnstark@sberdevices.=
ru> wrote:
>
> From: George Stark <GNStark@sberdevices.ru>
>
> According to datasheets of supported meson SOCs
> length of ADC_CLK_DIV field is 6 bits long
I have a question about this sentence which doesn't affect this patch
- it's only about managing expectations:
Which SoC are you referring to?
This divider is only relevant on older SoCs that predate GXBB (S905).
To my knowledge all SoCs from GXBB onwards place the divider in the
main or AO clock controller, so this bitmask is irrelevant there.

> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Aml=
ogic Meson SoCs")
> Signed-off-by: George Stark <GNStark@sberdevices.ru>
Since my question above doesn't affect this patch:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>