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Message-ID: <7772a5981d9a3d46056a53997162d1d75d22a701.camel@microchip.com>
Subject: Re: [PATCH] arm64: dts: microchip: add missing cache properties
From:   Steen Hegelund <steen.hegelund@microchip.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CC:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Lars Povlsen <lars.povlsen@microchip.com>,
        Daniel Machon <daniel.machon@microchip.com>,
        <UNGLinuxDriver@microchip.com>, <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
Date:   Wed, 17 May 2023 13:38:39 +0200
In-Reply-To: <151169f7-dcdb-47f1-9616-67c3c388a233@linaro.org>
References: <20230421223155.115339-1-krzysztof.kozlowski@linaro.org>
         <151169f7-dcdb-47f1-9616-67c3c388a233@linaro.org>
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Hi Krzysztof,

I would love to do that, but I am not familiar with the procedure, so maybe=
 you
could help me out?

This is my understanding of what I need to do:

Clone the upstream repo listed in MAINTAINERS:

git clone git@github.com:microchip-ung/linux-upstream.git
cd linux-upstream
git checkout sparx5-next

Fetch the latest mainline tag from upstream:

git fetch git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git =
tag\
 v6.4-rc2 --no-tags

Rebase the current branch on top of that tag:

git rebase v6.4-rc2

Use b4 to fetch and apply the mail thread patch series:

b4 shazam -tsl 20230421223155.115339-1-krzysztof.kozlowski@linaro.org

Tag the current work for inclusion in the next kernel version with a decrip=
tion:

git tag -s sparx5-dt-6.5

Push work that to the public repo:

git push origin sparx5-dt-6.5

Create a pull request (to stdout) to be included in an email to the maintai=
ners:

git request-pull v6.4-rc2 origin sparx5-dt-6.5

Send this PR to the maintainers and CC co-maintainers.

Is this the correct procedure?
Who should I send the PR email to (is there a list somewhere)?
=20
BR
Steen

On Tue, 2023-05-16 at 18:30 +0200, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know th=
e
> content is safe
>=20
> On 22/04/2023 00:31, Krzysztof Kozlowski wrote:
> > As all level 2 and level 3 caches are unified, add required
> > cache-unified and cache-level properties to fix warnings like:
> >=20
> > =C2=A0 sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required proper=
ty
> >=20
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >=20
> > ---
>=20
> Anyone from Microchip picking this up?
>=20
> Best regards,
> Krzysztof
>=20