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Date:   Wed, 17 May 2023 13:59:23 +0100
Message-ID: <86sfbvktas.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Yan =?UTF-8?B?WmhlbmfvvIjkuKXmlL/vvIk=?= <zhengyan@asrmicro.com>
Cc:     "tglx@linutronix.de" <tglx@linutronix.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Gao =?UTF-8?B?TWVpdGFv77yI6auY546r5rab77yJ?= 
        <meitaogao@asrmicro.com>,
        =?UTF-8?B?Ilpob3UgUWlhbyjlkajkvqgpIg==?= <qiaozhou@asrmicro.com>,
        =?UTF-8?B?IlpoYW5nIFpoaXpob3Uo5byg5rK75rSyKSI=?= 
        <zhizhouzhang@asrmicro.com>
Subject: Re: [PATCH] irqchip/gic-v3: workaround for ASR8601 when reading mpidr
In-Reply-To: <9dcef1c9343041c49a92ec8cd40d6331@exch03.asrmicro.com>
References: <20230517075500.43516-1-zhengyan@asrmicro.com>
        <86ttwbl5nq.wl-maz@kernel.org>
        <9dcef1c9343041c49a92ec8cd40d6331@exch03.asrmicro.com>
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On Wed, 17 May 2023 11:45:22 +0100,
Yan Zheng=EF=BC=88=E4=B8=A5=E6=94=BF=EF=BC=89 <zhengyan@asrmicro.com> wrote:
>=20
>=20
>=20
> > -----Original Message-----
> > From: Marc Zyngier [mailto:maz@kernel.org]
> > Sent: Wednesday, May 17, 2023 4:32 PM
> > To: Yan Zheng=EF=BC=88=E4=B8=A5=E6=94=BF=EF=BC=89 <zhengyan@asrmicro.co=
m>
> > Cc: tglx@linutronix.de; linux-kernel@vger.kernel.org; Gao Meitao=EF=BC=
=88=E9=AB=98=E7=8E=AB=E6=B6=9B=EF=BC=89
> > <meitaogao@asrmicro.com>; Zhou Qiao(=E5=91=A8=E4=BE=A8) <qiaozhou@asrmi=
cro.com>;
> > Zhang Zhizhou(=E5=BC=A0=E6=B2=BB=E6=B4=B2) <zhizhouzhang@asrmicro.com>
> > Subject: Re: [PATCH] irqchip/gic-v3: workaround for ASR8601 when reading
> > mpidr
> >=20
> > On Wed, 17 May 2023 08:55:00 +0100,
> > zhengyan <zhengyan@asrmicro.com> wrote:
> > >
> > > This patch add workaround for ASR8601, which uses an armv8.2 processor
> > > with a gic-500. ARMv8.2 uses Multiprocessor Affinity Register to
> > > identify the logical address of the core by
> > > | cluster | core | thread |.
> >=20
> > Not quite. The ARMv8.2 architecture doesn't say *any* of that. It is AR=
M's
> > *implementations* that follow this scheme.
> >=20
>=20
> Really thank you for rapid response,=20
> Yes, as arm documents
> https://developer.arm.com/docuentation/ka002107/latest said

This page doesn't exist.

> It comes from armv8.2 get 3 types for affinity (arm v8.0 cpus only get 2 =
types)
> And it's an implementations issue.

Again, this has nothing to do with the ARMv8.2 architecture. Nor the
ARMv8.0 architecture. Please read the ARM ARM, which says absolutely
*nothing* of what the various affinity levels are for.

>=20
> > > However, gic-500 only supports topologies with affinity levels less
> > > than 2 as
> > > | cluster | core|.
> > >
> > > So it needs this patch to shift the MPIDR values to ensure proper
> > > functionality
> > >
> > > Signed-off-by: zhengyan <zhengyan@asrmicro.com>
> > > ---
> > >  drivers/irqchip/irq-gic-v3.c | 28 +++++++++++++++++++++++++++-
> > >  1 file changed, 27 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/irqchip/irq-gic-v3.c
> > > b/drivers/irqchip/irq-gic-v3.c index 6fcee221f201..435b98a8641e 100644
> > > --- a/drivers/irqchip/irq-gic-v3.c
> > > +++ b/drivers/irqchip/irq-gic-v3.c
> > > @@ -39,6 +39,7 @@
> > >
> > >  #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996	(1ULL << 0)
> > >  #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539	(1ULL << 1)
> > > +#define FLAGS_WORKAROUND_MPIDR_ASR8601		(1ULL << 2)
> >=20
> > What is ASR8601? Is it a system? Or an erratum number? For issues that =
are the
> > result of a HW integration issue, please provide an official erratum nu=
mber, and
> > update Documentation/arm64/silicon-errata.rst.
> >=20
>=20
> ASR8601 is our soc's name, and yes it=E2=80=99s a kind of HW integration =
issue
> But maybe it=E2=80=99s not an erratum since our HW design is like that, a=
lthough
> Arm doesn't recommend this way.

Yes, for a good reason: it doesn't work. So this is *definitely* an
erratum, no ifs, no buts.

> And I would like to add more comments
> Under the next part before *desc	=3D "GICv3: ASR 8601 MPIDR shift"*
> Maybe this is a better way? Or add something under Documentation=EF=BC=9F

Documentation/arm64/silicon-errata.rst is the place to put it. Nowhere
else.

	M.

--=20
Without deviation from the norm, progress is not possible.