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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k16-20020a628410000000b0063d2130eadasi22716390pfd.256.2023.05.17.07.44.33; Wed, 17 May 2023 07:44:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20221208.gappssmtp.com header.s=20221208 header.b="kEBnaf/e"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232075AbjEQOgO (ORCPT + 99 others); Wed, 17 May 2023 10:36:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231617AbjEQOgH (ORCPT ); Wed, 17 May 2023 10:36:07 -0400 Received: from mail-ua1-x929.google.com (mail-ua1-x929.google.com [IPv6:2607:f8b0:4864:20::929]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D35B76B6 for ; Wed, 17 May 2023 07:36:01 -0700 (PDT) Received: by mail-ua1-x929.google.com with SMTP id a1e0cc1a2514c-783f7e82f2aso251491241.1 for ; Wed, 17 May 2023 07:36:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20221208.gappssmtp.com; s=20221208; t=1684334160; x=1686926160; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Lz5kmzNsavtOXsUzx7dQc9M1tds+op6IxOA3B91Azz0=; b=kEBnaf/eeVqzJkmoxSwK6peHNyQN+nMavdMcPVNxoA/YtqRfVXI/YUM+PZ/Lvc3wNS hVXtRBeuIU5EbJ1IMZzDkXNA5Oj4TgcaVDqrKTk4D5ExVb5yRgqQ/jSYVuORgpdNcL6L MriRQTXYJ8djpALImFTsuGEERsEO4WzcksyUR6fxdgxGap7urYQGvCNJxX7QRwxbsw+9 CNxiIV+lxfAGTWT5IwcQzOQ/8Hhblhdo+QASH2ZeFU+nrCllHccOnGK1VQ2yeXaau2sS +BjDsLgVzY373Lyi1WQ836Uz40dDJMKhdT4MnLExI/q5+fS+Yabqba2a2LP/n9KgdFVz u7hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684334160; x=1686926160; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lz5kmzNsavtOXsUzx7dQc9M1tds+op6IxOA3B91Azz0=; b=gHLPFtKk9MR+2YYgj3WOrcA97l/awOns/TjIsAd+x5WWo7nzem5EBgAE+v+4DIzVtW 0ITAb9HwndrJkKj6RagNgCJOjc5AtrRLDs7NwutARl6BuPB3LFJdJs57WhDMidMRaSGV wNTAX54ETFYYiLamqpQXlY/hiWEx+y6s0dfBkdVwbvXTFrfHFi8cVkXWpRPgB6oGVVgh NHQZSrdaxhOWoTV3SpYEivxG3jX2ZTo+4gwUbIifGG2hnO5DUqLIkxVEhQppjnswyS1C VmiR0/He75CctRETeIsMLtHf6jDUJuVmdSbXEykVARfW1JqaOj060snnum5K7h/nK7O4 v5EQ== X-Gm-Message-State: AC+VfDy11UTHXwt3IjbV0rmXH3KoaY4eXQHJaHut+koY4Jh0cRkb2a/W F4/mGU0UXhf9iswfpD0SqyddhNGVG0MQWBEijvNbsscL6bFECslF X-Received: by 2002:a05:6102:2ed:b0:434:6f77:4f62 with SMTP id j13-20020a05610202ed00b004346f774f62mr15827147vsj.1.1684334160192; Wed, 17 May 2023 07:36:00 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Bartosz Golaszewski Date: Wed, 17 May 2023 16:35:49 +0200 Message-ID: Subject: Re: [PATCH 2/3] gpio: 104-dio-48e: Add Counter/Timer support To: William Breathitt Gray Cc: Linus Walleij , Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Apr 16, 2023 at 7:37=E2=80=AFPM William Breathitt Gray wrote: > > The 104-DIO-48E features an 8254 Counter/Timer chip providing three > counter/timers which can be used for frequency measurement, frequency > output, pulse width modulation, pulse width measurement, event count, > etc. The counter/timers use the same addresses as PPI 0 (addresses 0x0 > to 0x3), so a raw_spinlock_t is used to synchronize operations between > the two regmap mappings to prevent clobbering. > > Signed-off-by: William Breathitt Gray Looks good to me. Let me know when you have an immutable tag to pull. Bart