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Wed, 17 May 2023 08:03:36 -0700 Received: from [10.41.21.79] (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 17 May 2023 08:03:32 -0700 Message-ID: Date: Wed, 17 May 2023 20:33:30 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 1/2] cpufreq: CPPC: keep target core awake when reading its cpufreq rate To: Pierre Gondois , Zeng Heng , Ionela Voinescu CC: , , , , , , , , , , Yang Shi References: <20230516133248.712242-1-zengheng4@huawei.com> Content-Language: en-US From: Sumit Gupta In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT074:EE_|DM4PR12MB5746:EE_ X-MS-Office365-Filtering-Correlation-Id: e918fc10-3e5a-43f1-854d-08db56e7ec26 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2023 15:03:50.0563 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e918fc10-3e5a-43f1-854d-08db56e7ec26 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5746 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, NICE_REPLY_A,SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/05/23 13:47, Pierre Gondois wrote: > External email: Use caution opening links or attachments > > > +Ionela, Sumit, Yang, > > Hello Zeng, > > I think solutions around related issues were suggested at: > > [1] https://lore.kernel.org/all/20230418113459.12860-7-sumitg@nvidia.com/ > [2] > https://lore.kernel.org/all/20230328193846.8757-1-yang@os.amperecomputing.com/ > [3] https://lore.kernel.org/all/ZEl1Fms%2FJmdEZsVn@arm.com/ > > About this patch, it seems to mean that CPPC counters of CPUx are always > accessed from CPUx, even when they are not AMUs. For instance CPPC > counters could be memory mapped and accessible from any CPU. > cpu_has_amu_feat() should allow to probe if a CPU uses AMUs or not, > and [2] had an implementation using it. > > Another comment about PATCH 2/2 is that if the counters are accessed > through FFH, arm64 version of cpc_read_ffh() is calling > counters_read_on_cpu(), and a comment in counters_read_on_cpu() seems > to specify the function must be called with interrupt enabled. > > I think the best solution so far was the one at [3], suggested by Ionela, > but it doesn't seem to solve your issue. Indeed, it is not checked whether > the counters are AMU counters and that they must be remotely read (to > have the CPU awake), > > Regards, > Pierre > I think the solution in [1] is simple and solves all the three cases. Also, it provides better accuracy between the set and get frequency as compared to [3]. This can be merged and can later still be improved in Upstream. If OK, I can send new version by changing the patch to apply for all ARM SoC's with AMU and not specific to Tegra. Thank you, Sumit Gupta > > On 5/16/23 15:32, Zeng Heng wrote: >> As ARM AMU's document says, all counters are subject to any changes >> in clock frequency, including clock stopping caused by the WFI and WFE >> instructions. >> >> Therefore, using smp_call_on_cpu() to trigger target CPU to >> read self's AMU counters, which ensures the counters are working >> properly during calculation. >> >> Signed-off-by: Zeng Heng >> --- >>   drivers/cpufreq/cppc_cpufreq.c | 30 +++++++++++++++++++----------- >>   1 file changed, 19 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/cpufreq/cppc_cpufreq.c >> b/drivers/cpufreq/cppc_cpufreq.c >> index 022e3555407c..910167f58bb3 100644 >> --- a/drivers/cpufreq/cppc_cpufreq.c >> +++ b/drivers/cpufreq/cppc_cpufreq.c >> @@ -837,9 +837,24 @@ static int cppc_perf_from_fbctrs(struct >> cppc_cpudata *cpu_data, >>       return (reference_perf * delta_delivered) / delta_reference; >>   } >> >> +static int cppc_get_perf_ctrs_smp(void *val) >> +{ >> +     int cpu = smp_processor_id(); >> +     struct cppc_perf_fb_ctrs *fb_ctrs = val; >> +     int ret; >> + >> +     ret = cppc_get_perf_ctrs(cpu, fb_ctrs); >> +     if (ret) >> +             return ret; >> + >> +     udelay(2); /* 2usec delay between sampling */ >> + >> +     return cppc_get_perf_ctrs(cpu, fb_ctrs + 1); >> +} >> + >>   static unsigned int cppc_cpufreq_get_rate(unsigned int cpu) >>   { >> -     struct cppc_perf_fb_ctrs fb_ctrs_t0 = {0}, fb_ctrs_t1 = {0}; >> +     struct cppc_perf_fb_ctrs fb_ctrs[2] = {0}; >>       struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); >>       struct cppc_cpudata *cpu_data = policy->driver_data; >>       u64 delivered_perf; >> @@ -847,19 +862,12 @@ static unsigned int >> cppc_cpufreq_get_rate(unsigned int cpu) >> >>       cpufreq_cpu_put(policy); >> >> -     ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t0); >> -     if (ret) >> -             return ret; >> - >> -     udelay(2); /* 2usec delay between sampling */ >> - >> -     ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t1); >> +     ret = smp_call_on_cpu(cpu, cppc_get_perf_ctrs_smp, fb_ctrs, 1); >>       if (ret) >>               return ret; >> >> -     delivered_perf = cppc_perf_from_fbctrs(cpu_data, &fb_ctrs_t0, >> -                                            &fb_ctrs_t1); >> - >> +     delivered_perf = cppc_perf_from_fbctrs(cpu_data, fb_ctrs, >> +                                            fb_ctrs + 1); >>       return cppc_cpufreq_perf_to_khz(cpu_data, delivered_perf); >>   } >>