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[93.5.22.158]) by smtp.gmail.com with ESMTPSA id u15-20020adfed4f000000b00307c46f4f08sm3267555wro.79.2023.05.17.09.52.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 May 2023 09:52:58 -0700 (PDT) Message-ID: <94f8af4a-2555-052d-d04a-a0e54e0e2d13@baylibre.com> Date: Wed, 17 May 2023 18:52:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 0/2] clk/mediatek: Adjustments for MSDC rate accuracy To: AngeloGioacchino Del Regno , mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, wenst@chromium.org, chun-jie.chen@mediatek.com, mandyjh.liu@mediatek.com, miles.chen@mediatek.com, zhaojh329@gmail.com, daniel@makrotopia.org, nfraprado@collabora.com, rex-bc.chen@mediatek.com, Garmin.Chang@mediatek.com, msp@baylibre.com, yangyingliang@huawei.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com References: <20230516135205.372951-1-angelogioacchino.delregno@collabora.com> Content-Language: en-US From: Alexandre Mergnat In-Reply-To: <20230516135205.372951-1-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/05/2023 15:52, AngeloGioacchino Del Regno wrote: > Changes in v2: > - Extended the changes in this series to MT8365 clocks > > This series stops unconditionally forcing CLK_SET_RATE_PARENT on > MediaTek muxes, as that should be set in the clock driver for each > clock requiring it, and removes CLK_SET_PARENT from all MSDC core > clocks to allow mtk-sd to select the right clock parent when doing > mclk setting, improving the rate accuracy and avoiding both under > and overclocks of the eMMC/SD/SDIO card, both improving performance > and stability of the attached storage. > > This series was successfully tested on MT8173, MT8192, MT8195. > > AngeloGioacchino Del Regno (2): > clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag > clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks > > drivers/clk/mediatek/clk-mt6765.c | 20 +++++----- > drivers/clk/mediatek/clk-mt6779.c | 24 +++++------ > drivers/clk/mediatek/clk-mt7981-topckgen.c | 12 +++--- > drivers/clk/mediatek/clk-mt7986-topckgen.c | 12 +++--- > drivers/clk/mediatek/clk-mt8173-topckgen.c | 24 +++++------ > drivers/clk/mediatek/clk-mt8183.c | 22 ++++++----- > drivers/clk/mediatek/clk-mt8186-topckgen.c | 24 +++++------ > drivers/clk/mediatek/clk-mt8188-topckgen.c | 40 +++++++++++-------- > drivers/clk/mediatek/clk-mt8192.c | 23 +++++------ > drivers/clk/mediatek/clk-mt8195-topckgen.c | 46 +++++++++++++--------- > drivers/clk/mediatek/clk-mt8365.c | 38 +++++++++--------- > drivers/clk/mediatek/clk-mux.c | 2 +- > 12 files changed, 155 insertions(+), 132 deletions(-) > I will try to test it next week on MT8365 SoC. -- Regards, Alexandre