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From:   =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
To:     David Hildenbrand <david@redhat.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org
Cc:     =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>,
        linux-kernel@vger.kernel.org, linux-mm@kvack.org,
        Oscar Salvador <osalvador@suse.de>,
        virtualization@lists.linux-foundation.org, linux@rivosinc.com,
        Alexandre Ghiti <alexghiti@rivosinc.com>
Subject: Re: [PATCH 0/7] riscv: Memory Hot(Un)Plug support
In-Reply-To: <9aa7d030-19b5-01df-70c0-86d8d6ab86a6@redhat.com>
References: <20230512145737.985671-1-bjorn@kernel.org>
 <9aa7d030-19b5-01df-70c0-86d8d6ab86a6@redhat.com>
Date:   Wed, 17 May 2023 20:53:55 +0200
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David Hildenbrand <david@redhat.com> writes:

> On 12.05.23 16:57, Bj=C3=B6rn T=C3=B6pel wrote:
>> From: Bj=C3=B6rn T=C3=B6pel <bjorn@rivosinc.com>
>>=20
>> Memory Hot(Un)Plug support for the RISC-V port
>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

[...]

>
> Cool stuff! I'm fairly busy right now, so some high-level questions upfro=
nt:

No worries, and no rush! I'd say the v1 series was mainly for the RISC-V
folks, and I've got tons of (offline) comments from Alex -- and with
your comments below some more details to figure out.

> What is the memory section size (which implies the memory block size=20
> and)? This implies the minimum DIMM granularity and the high-level=20
> granularity in which virtio-mem adds memory.

It's 128M (27 bits) -- (like arm64 and x86-64?).

> What is the pageblock size, implying the minimum granularity that=20
> virtio-mem can operate on?

Nothing special AFAIU; MAX_ORDER is 10, so PAGE_SIZE (4K) * 1024. Hmm, I
realize that I need to look into some more details of virtio-mem! :-)

> On x86-64 and arm64 we currently use the ACPI SRAT to expose the maximum=
=20
> physical address where we can see memory getting hotplugged. [1] From=20
> that, we can derive the "max_possible_pfn" and prepare the kernel=20
> virtual memory layourt (especially, direct map).
>
> Is something similar required on RISC-V?

Yes! RISC-V is in the progress of getting proper ACPI support. Thanks
for pointing me in the these directions; Food for thought that I'll
digest for the next version.


Cheers,
Bj=C3=B6rn