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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w2-20020a627b02000000b00643a695e976si71711pfc.291.2023.05.17.15.35.18; Wed, 17 May 2023 15:35:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229880AbjEQWOt (ORCPT + 99 others); Wed, 17 May 2023 18:14:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbjEQWOs (ORCPT ); Wed, 17 May 2023 18:14:48 -0400 Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [IPv6:2001:4b7a:2000:18::163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62CE135A9 for ; Wed, 17 May 2023 15:14:46 -0700 (PDT) Received: from SoMainline.org (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 92AFC2047B; Thu, 18 May 2023 00:14:41 +0200 (CEST) Date: Thu, 18 May 2023 00:14:38 +0200 From: Marijn Suijten To: Kuogee Hsieh Cc: dri-devel@lists.freedesktop.org, robdclark@gmail.com, sean@poorly.run, swboyd@chromium.org, dianders@chromium.org, vkoul@kernel.org, daniel@ffwll.ch, airlied@gmail.com, agross@kernel.org, dmitry.baryshkov@linaro.org, andersson@kernel.org, Abhinav Kumar , quic_jesszhan@quicinc.com, quic_sbillaka@quicinc.com, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v10 1/8] drm/msm/dpu: add dsc blocks to the catalog of MSM8998 and SC8180X Message-ID: References: <1684360919-28458-1-git-send-email-quic_khsieh@quicinc.com> <1684360919-28458-2-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1684360919-28458-2-git-send-email-quic_khsieh@quicinc.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DSC* in the title. On 2023-05-17 15:01:52, Kuogee Hsieh wrote: > From: Abhinav Kumar > > Some platforms have DSC blocks which have not been declared in the catalog. > Complete DSC 1.1 support for all platforms by adding the missing blocks to > MSM8998 and SC8180X. > > Changes in v9: > -- add MSM8998 and SC8180x to commit titil title* (couldn't be caught in v9... because this changelog wasn't present then) - Marijn > > Changes in v10: > -- fix grammar at commit text > > Signed-off-by: Abhinav Kumar > Reviewed-by: Dmitry Baryshkov > Reviewed-by: Marijn Suijten > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++++++ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 11 +++++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > index c0dd477..521cfd5 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > @@ -126,6 +126,11 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > }; > > +static const struct dpu_dsc_cfg msm8998_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), > + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), > +}; > + > static const struct dpu_dspp_cfg msm8998_dspp[] = { > DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, > &msm8998_dspp_sblk), > @@ -199,6 +204,8 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { > .dspp = msm8998_dspp, > .pingpong_count = ARRAY_SIZE(msm8998_pp), > .pingpong = msm8998_pp, > + .dsc_count = ARRAY_SIZE(msm8998_dsc), > + .dsc = msm8998_dsc, > .intf_count = ARRAY_SIZE(msm8998_intf), > .intf = msm8998_intf, > .vbif_count = ARRAY_SIZE(msm8998_vbif), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > index e8057a1..fec1665 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > @@ -142,6 +142,15 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > }; > > +static const struct dpu_dsc_cfg sc8180x_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)), > +}; > + > static const struct dpu_intf_cfg sc8180x_intf[] = { > INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), > @@ -206,6 +215,8 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { > .mixer = sc8180x_lm, > .pingpong_count = ARRAY_SIZE(sc8180x_pp), > .pingpong = sc8180x_pp, > + .dsc_count = ARRAY_SIZE(sc8180x_dsc), > + .dsc = sc8180x_dsc, > .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), > .merge_3d = sc8180x_merge_3d, > .intf_count = ARRAY_SIZE(sc8180x_intf), > -- > 2.7.4 >