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From:   "Havalige, Thippeswamy" <thippeswamy.havalige@amd.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        "bhelgaas@google.com" <bhelgaas@google.com>,
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        "Gogada, Bharat Kumar" <bharat.kumar.gogada@amd.com>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>
Subject: RE: [PATCH v2 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
Thread-Topic: [PATCH v2 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port
 driver
Thread-Index: AQHZhJrntUaPjNRHKk2++3mbbOWIBK9XB9EAgAh5VFA=
Date:   Thu, 18 May 2023 04:58:38 +0000
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References: <20230512062725.1208385-4-thippeswamy.havalige@amd.com>
 <ZF6UWBd0x9LxAhoJ@bhelgaas>
In-Reply-To: <ZF6UWBd0x9LxAhoJ@bhelgaas>
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Hi Bjorn,

Regards,
Thippeswamy H
> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Saturday, May 13, 2023 1:03 AM
> To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>
> Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; krzysztof.kozlowski@linaro.org;
> bhelgaas@google.com; michals@xilinx.com; robh+dt@kernel.org;
> Yeleswarapu, Nagaradhesh <nagaradhesh.yeleswarapu@amd.com>; Gogada,
> Bharat Kumar <bharat.kumar.gogada@amd.com>;
> lorenzo.pieralisi@arm.com
> Subject: Re: [PATCH v2 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port d=
river
>=20
> On Fri, May 12, 2023 at 11:57:25AM +0530, Thippeswamy Havalige wrote:
> > Add support for Xilinx XDMA Soft IP core as Root Port.
> > ...
>=20
> > +#include <linux/of_pci.h>
> > +#include <linux/irqchip/chained_irq.h>
>=20
> The trend seems to be to alphabetize the system includes above.
- Agreed, fix it in next patch
> > +#include "pcie-xilinx-common.h"
> > +
> > +#include "../pci.h"
- Agreed, fix it in next patch
> Put the pcie-xilinx-common.h include here, as you did for
> pcie-xilinx-cpm.c:
>=20
>   #include <linux/irqchip/chained_irq.h>
>=20
>   #include "../pci.h"
>   #include "pcie-xilinx-common.h"
- Agreed, fix it in next patch
> pcie-xilinx.c has a very similar list of register definitions, which make=
s me
> wonder why it can't share pcie-xilinx-common.h as well.
>=20
> Obviously it would take a bit of rework since it uses BIT(x) instead of j=
ust "x".
> But you hide the "BIT()" inside IMR(), which is arguably slightly obscure=
 since
> the #define value is not a register mask:
>=20
> > +#define IMR(x) BIT(XILINX_PCIE_INTR_ ##x)
>=20
> I don't really care either way, but it seems like a possibly needless dif=
ference.
> Bjorn