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Thu, 18 May 2023 18:06:16 +0000 Date: Thu, 18 May 2023 11:06:11 -0700 From: David Zheng To: , CC: , , , Subject: [PATCH] i2c: designware: fix idx_write_cnt in read loop Message-ID: Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-ClientProxiedBy: BYAPR21CA0003.namprd21.prod.outlook.com (2603:10b6:a03:114::13) To DM6PR11MB3004.namprd11.prod.outlook.com (2603:10b6:5:67::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6PR11MB3004:EE_|SJ0PR11MB5088:EE_ X-MS-Office365-Filtering-Correlation-Id: b0182860-9d34-43a6-e5a5-08db57ca92ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3Zii27UFcdO3XBmJh/6ZRGayIc5UFbVhhAFcbn+3cEO/RE82ngmwziAyFPcbltMCBEZ0j9JIa3K8RQdF0pxiqyDal307GgRGk2W+kzeXq/BTIqv59XtyNSgCZDmB+ZzCYOUP+6sha6UxQW4pfFt5EroB2/BxJU/MWhi8HuYr4LNhrNfkQF3hrbRJB6SoKdKe17CT+bYRuRMrXBcn6OXknxWl5Ofz2tOOSTUkLRwB/FicaGW9XnNpMZzIPlvakAjgPPIUUBQKT6vAsRqfp5iqEB+XTsZeT+TO5GCR7IOzIOXcU2AIIIrfKhxedENnErcECAUtPaQT9y9VCKXQIwVaxui0pJCRSFj0IiY9Lf44Um9BFBfMKELs6gAlNWYS0lYT07Them8jyeBnIm6oe05hDpUkw26X21EJkSYQ3X7iSKRM7qNmZreOEMkzyUaIPbjes7rr/CIRAC7x87jyPSeI0eOziGVEcSbtiWaP2dVl8bwqZOxz5Oh1j1739HyzGyUrvuMkBURXZIygrsT7zOJzNgSCYHyIY998llET0x8RkV0FOrbsB9P8RFle/vBNeal1 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM6PR11MB3004.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(7916004)(136003)(39860400002)(346002)(396003)(376002)(366004)(451199021)(33716001)(6666004)(4326008)(66476007)(478600001)(41300700001)(66556008)(66946007)(6486002)(316002)(86362001)(6506007)(83380400001)(6512007)(38100700002)(26005)(186003)(82960400001)(9686003)(8676002)(2906002)(44832011)(5660300002)(8936002);DIR:OUT;SFP:1102; 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When testing with the slave-eeprom, each transaction has 2 bytes for address/index and 1 byte for value, the address byte can be written as data byte due to dropping STOP condition. In the test below, the master continuously writes to the slave, first 2 bytes are index, 3rd byte is value and follow by a STOP condition. i2c_write: i2c-3 #0 a=04b f=0000 l=3 [00-D1-D1] i2c_write: i2c-3 #0 a=04b f=0000 l=3 [00-D2-D2] i2c_write: i2c-3 #0 a=04b f=0000 l=3 [00-D3-D3] Upon receiving STOP condition slave eeprom would reset `idx_write_cnt` so next 2 bytes can be treated as buffer index for upcoming transaction. Supposedly the slave eeprom buffer would be written as EEPROM[0x00D1] = 0xD1 EEPROM[0x00D2] = 0xD2 EEPROM[0x00D3] = 0xD3 When CPU load is high the slave irq handler may not read fast enough, the interrupt status can be seen as 0x204 with both DW_IC_INTR_STOP_DET (0x200) and DW_IC_INTR_RX_FULL (0x4) bits. The slave device may see the transactions below. 0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x1594 : INTR_STAT=0x4 0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x1594 : INTR_STAT=0x4 0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x1594 : INTR_STAT=0x4 0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x1794 : INTR_STAT=0x204 0x1 STATUS SLAVE_ACTIVITY=0x0 : RAW_INTR_STAT=0x1790 : INTR_STAT=0x200 0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x1594 : INTR_STAT=0x4 0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x1594 : INTR_STAT=0x4 0x1 STATUS SLAVE_ACTIVITY=0x1 : RAW_INTR_STAT=0x1594 : INTR_STAT=0x4 After `D1` is received, read loop continues to read `00` which is the first bype of next index. Since STOP condition is ignored by the loop, eeprom buffer index increased to `D2` and `00` is written as value. So the slave eeprom buffer becomes EEPROM[0x00D1] = 0xD1 EEPROM[0x00D2] = 0x00 EEPROM[0x00D3] = 0xD3 The fix is to use `FIRST_DATA_BYTE` (bit 11) in `IC_DATA_CMD` to split the transactions. The first index byte in this case would have bit 11 set. Check this indication to inject I2C_SLAVE_WRITE_REQUESTED event which will reset `idx_write_cnt` in slave eeprom. Signed-off-by: David Zheng --- drivers/i2c/busses/i2c-designware-core.h | 2 ++ drivers/i2c/busses/i2c-designware-slave.c | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index c5d87aae39c6..8b85147bd518 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -123,6 +123,8 @@ #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) +#define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11) + /* * Sofware status flags */ diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses/i2c-designware-slave.c index cec25054bb24..9549cbcf50aa 100644 --- a/drivers/i2c/busses/i2c-designware-slave.c +++ b/drivers/i2c/busses/i2c-designware-slave.c @@ -170,12 +170,14 @@ static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id) if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { dev->status |= STATUS_WRITE_IN_PROGRESS; dev->status &= ~STATUS_READ_IN_PROGRESS; - i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, - &val); } do { regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); + if (tmp & DW_IC_DATA_CMD_FIRST_DATA_BYTE) + i2c_slave_event(dev->slave, + I2C_SLAVE_WRITE_REQUESTED, + &val); val = tmp; i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED, &val); -- 2.40.1