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Received: from SN6PR12MB2621.namprd12.prod.outlook.com (2603:10b6:805:73::15) by CH2PR12MB4054.namprd12.prod.outlook.com (2603:10b6:610:a6::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6411.17; Thu, 18 May 2023 18:37:35 +0000 Received: from SN6PR12MB2621.namprd12.prod.outlook.com ([fe80::8018:78f7:1b08:7a54]) by SN6PR12MB2621.namprd12.prod.outlook.com ([fe80::8018:78f7:1b08:7a54%2]) with mapi id 15.20.6411.019; Thu, 18 May 2023 18:37:35 +0000 Message-ID: <0b358a84-511f-f607-336d-9d5b49068972@amd.com> Date: Thu, 18 May 2023 19:37:26 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: Need suggestions for smp related properties in cpus.yaml to support smpboot for cortex-r52 based platform To: Sudeep Holla Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, geert+renesas@glider.be, magnus.damm@gmail.com, konrad.dybcio@linaro.org, andersson@kernel.org, mazziesaccount@gmail.com, conor.dooley@microchip.com, j@jannau.net, mailingradian@gmail.com, me@iskren.info, lpieralisi@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Julien Grall , Stefano Stabellini , Michal Orzel , Michal Simek References: <20230515100810.ctebdbqlienbcf7t@bogus> From: Ayan Kumar Halder In-Reply-To: <20230515100810.ctebdbqlienbcf7t@bogus> Content-Type: text/plain; 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What happened to that ? Any summary why that was dropped ? We are discussing internally with other Xilinx/AMD engineers about this. > >> I was discussing with xen-devel community about how we can properly support >> smpboot when I was suggested that this might be the correct forum for >> discussion. >> >> Please refer >> https://lists.xenproject.org/archives/html/xen-devel/2023-05/msg00224.html >> and the follow-ups for context. >> >> >> The way smpboot works on our platform is as follows:- >> >> 1. core0 writes to register (say regA) the address of the secondary core >> initialization routine. >> >> 2. core0 writes to another register (say regB) the value "0x1" to put the >> secondary core in reset mode. >> >> 3. core0 writes to regB the value "0x0" to pull the secondary core out of >> reset mode. >> >> regA, regB will differ for core1, core2, core3 and so on. >> > Sounds OK but will you ever need to support power management on these cores ? > If so, just start with PSCI or provide reasons as why it doesn't fit well > before exploring and extending the existing spin table bindings. Power management is not in scope. About PSCI, we are discussing internally. > >> Currently, I am trying to bringup core1 only. >> >> >> I am thinking to use "enable-method=spin-table" in the cpu node for core1. >> So that I can use "cpu-release-address" for regA. >> >> For regB, I am thinking of introducing a new property "amd-cpu-reset-addr" >> in the cpu node. >> >> Please let me know your thoughts on this approach. I am also open to any >> alternative suggestions. >> >> >> Also I see that in https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/devicetree/bindings/arm/cpus.yaml#L87 >> , "arm,cortex-r52" is missing. >> > Yes that should be fine IMO. > >> Can I submit a patch (a one line change) to add this ? >> > Of course, it makes it easy to accept or reject rather than this question > hidden as part of other discussion. I have submitted a patch for this. https://archive.armlinux.org.uk/lurker/message/20230518.152730.c91cc994.en.html - Ayan > > -- > Regards, > Sudeep