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Thu, 18 May 2023 19:00:30 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34IJ0TJU004567 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 19:00:29 GMT Received: from [10.110.94.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 18 May 2023 12:00:28 -0700 Message-ID: Date: Thu, 18 May 2023 12:00:22 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v10 7/8] drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets Content-Language: en-US To: Marijn Suijten CC: Kuogee Hsieh , , , , , , , , , , , , , References: <1684360919-28458-1-git-send-email-quic_khsieh@quicinc.com> <1684360919-28458-8-git-send-email-quic_khsieh@quicinc.com> <51f0439c-a5e8-b47a-21af-7bbbc944ca53@quicinc.com> From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DdZrgPMEsRUJyHf0_xuaTq1OLTne6mqZ X-Proofpoint-GUID: DdZrgPMEsRUJyHf0_xuaTq1OLTne6mqZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-18_14,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 impostorscore=0 mlxlogscore=800 priorityscore=1501 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305180156 X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/18/2023 12:05 AM, Marijn Suijten wrote: > On 2023-05-17 16:22:37, Abhinav Kumar wrote: > >>>> @@ -529,6 +539,19 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { >>>> .features = _features, \ >>>> } >>>> >>>> +/* >>>> + * NOTE: Each display compression engine (DCE) contains dual hard >>>> + * slice DSC encoders so both share same base address but with >>>> + * its own different sub block address. >>>> + */ >>> >>> I still think this comment is superfluous (and doesn't even apply >>> generically, see i.e. sc7280) and should best be kept exclusively in the >>> SoC-specific catalog files. >>> >>> - Marijn >>> >> >> sc7280 is the only exception as it has only one encoder. But, by and >> large, for all other chipsets this is true and hence kept here. >> >> The main reason for this comment is people should not get confused that >> how come two DSC encoders have the same base address. > > And that's why the comment is already placed in the SoC-specific catalog > files where a duplicate base address is visible. It is not visible > here. > > - Marijn > ok, if kuogee pushes a v11, we can drop it. >>>> +#define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \ >>>> + {\ >>>> + .name = _name, .id = _id, \ >>>> + .base = _base, .len = _len, \ >>>> + .features = BIT(DPU_DSC_HW_REV_1_2) | _features, \ >>>> + .sblk = &_sblk, \ >>>> + } >>>> + >>>> /************************************************************* >>>> * INTF sub blocks config >>>> *************************************************************/ >>>> -- >>>> 2.7.4 >>>>