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Subject: Re: [PATCH 1/3] MIPS: Introduce WAR_4KC_LLSC config option
From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
In-Reply-To: <alpine.DEB.2.21.2305192117230.50034@angie.orcam.me.uk>
Date:   Fri, 19 May 2023 22:51:04 +0100
Cc:     "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        linux-kernel@vger.kernel.org,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Message-Id: <53043C18-7C75-4D5F-A15E-86D981D19CA8@flygoat.com>
References: <20230519164753.72065-1-jiaxun.yang@flygoat.com>
 <20230519164753.72065-2-jiaxun.yang@flygoat.com>
 <alpine.DEB.2.21.2305192117230.50034@angie.orcam.me.uk>
To:     "Maciej W. Rozycki" <macro@orcam.me.uk>
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> 2023=E5=B9=B45=E6=9C=8819=E6=97=A5 21:23=EF=BC=8CMaciej W. Rozycki =
<macro@orcam.me.uk> =E5=86=99=E9=81=93=EF=BC=9A
>=20
> On Fri, 19 May 2023, Jiaxun Yang wrote:
>=20
>> diff --git a/arch/mips/kernel/cpu-probe.c =
b/arch/mips/kernel/cpu-probe.c
>> index 6d15a398d389..fd452e68cd90 100644
>> --- a/arch/mips/kernel/cpu-probe.c
>> +++ b/arch/mips/kernel/cpu-probe.c
>> @@ -152,6 +152,13 @@ static inline void check_errata(void)
>> struct cpuinfo_mips *c =3D &current_cpu_data;
>>=20
>> switch (current_cpu_type()) {
>> + case CPU_4KC:
>> + if ((c->processor_id & PRID_REV_MASK) < PRID_REV_4KC_V1_0) {
>> + c->options &=3D ~MIPS_CPU_LLSC;
>> + if (!IS_ENABLED(CONFIG_WAR_4K_LLSC))
>> + pr_err("CPU have LLSC errata, please enable CONFIG_WAR_4K_LLSC");
>=20
> Given the circumstances I think this should be `panic'.  You don't =
want=20
> to continue with a system that can randomly lock up.

I just checked how other architectures handle such situation, it seems =
like
TAINT_CPU_OUT_OF_SPEC is a better option.

Panic in cpu_probe can be frustrating for users as it is earlier than =
initialisation
of consoles so the panic message can never be read by users.

>=20
> Also "CPU has LLSC erratum, [...]" as both are singular.

Thanks for the tip :-)
- Jiaxun

>=20
>  Maciej