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Subject: Re: [PATCH] MIPS: Fix MIPS_O32_FP64_SUPPORT for 64bit CPUs before R2
From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
In-Reply-To: <alpine.DEB.2.21.2305192033550.50034@angie.orcam.me.uk>
Date:   Fri, 19 May 2023 23:02:47 +0100
Cc:     "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        linux-kernel@vger.kernel.org,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Message-Id: <C1676532-0051-43D7-82D8-1E5697407C70@flygoat.com>
References: <20230519163023.70542-1-jiaxun.yang@flygoat.com>
 <alpine.DEB.2.21.2305192033550.50034@angie.orcam.me.uk>
To:     "Maciej W. Rozycki" <macro@orcam.me.uk>
Precedence: bulk


> 2023=E5=B9=B45=E6=9C=8819=E6=97=A5 21:10=EF=BC=8CMaciej W. Rozycki =
<macro@orcam.me.uk> =E5=86=99=E9=81=93=EF=BC=9A
>=20
> On Fri, 19 May 2023, Jiaxun Yang wrote:
>=20
>> MIPS_O32_FP64_SUPPORT enables possibility of using all 32 FPRs on =
32bit
>> kernel in case CPU implemented FR1. As FR1 is present on all 64bit =
CPUs
>> following R4000's priviliged spec, there is no reason to limit such =
support
>> to R2+ CPUs.
>=20
> I guess one can do it and still run FPXX software, but I fail to see =
what=20
> gain it provides.  For FP32 it breaks things as accesses to =
odd-numbered=20
> FPRs will no longer get at the high part of a double value and for =
FP64=20
> there are no MTHC1/MFHC1 instructions required to access the high =
part.

Actually software may access the high part by SDC1/LDC1.
FP32 binaries are still going to run at FR0 mode.

>=20
> What problem are you trying to solve?  And how did you verify this =
patch?

Was trying to deal a proprietary JIT software who want to enable FR1 via =
prctl
on Loongson-2F with 32 bit kernel.

>=20
>> --- a/arch/mips/kernel/fpu-probe.c
>> +++ b/arch/mips/kernel/fpu-probe.c
>> @@ -289,6 +289,23 @@ void cpu_set_fpu_opts(struct cpuinfo_mips *c)
>> c->options |=3D MIPS_CPU_FRE;
>> }
>>=20
>> + /* Fix up FIR for FPU earlier than R2 */
>> + if (!cpu_has_mips_r2_r6) {
>> + c->fpu_id |=3D MIPS_FPIR_S;
>> +#ifdef CONFIG_CPU_R4K_FPU
>> + /* All known R4000 class FPU implemented double */
>> + c->fpu_id |=3D MIPS_FPIR_D;
>> +#endif
>=20
> Currently all FPUs we support implement double and we require that, so =
no=20
> need to make this piece conditional (I would use IS_ENABLED otherwise, =
so=20
> as not to clutter the source with #ifdef), but `c->fpu_id' is also =
exposed=20
> to the user via ptrace(2), so this has to reflect hardware and not =
give a=20
> synthesized value.

Alas, I thought R2030 class FPU does not have double? Since MIPS-IV spec
says SDC1 is introduced in MIPS II.

Thanks
Jiaxun

>=20
>  Maciej