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From:   Adam Ford <aford173@gmail.com>
Date:   Fri, 19 May 2023 17:04:01 -0500
Message-ID: <CAHCN7xKHHKQgjtzS+KSHE9w++_udRJ1PRVcse=rD6-tZGVGcdQ@mail.gmail.com>
Subject: Re: [PATCH] clk: imx: composite-8m: Add imx8m_divider_determine_rate
To:     linux-clk@vger.kernel.org
Cc:     aford@beaconembedded.com, Abel Vesa <abelvesa@kernel.org>,
        Peng Fan <peng.fan@nxp.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>
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On Thu, May 11, 2023 at 10:03=E2=80=AFPM Adam Ford <aford173@gmail.com> wro=
te:
>
> On Sat, May 6, 2023 at 2:53=E2=80=AFPM Adam Ford <aford173@gmail.com> wro=
te:
> >
> > Currently, certain clocks are derrived as a divider from their
> > parent clock.  For some clocks, even when CLK_SET_RATE_PARENT
> > is set, the parent clock is not properly set which can lead
> > to some relatively inaccurate clock values.
> >
> > Unlike imx/clk-composite-93 and imx/clk-divider-gate, it
> > cannot rely on calling a standard determine_rate function,
> > because the 8m composite clocks have a pre-divider and
> > post-divider. Because of this, a custom determine_rate
> > function is necessary to determine the maximum clock
> > division which is equivalent to pre-divider * the
> > post-divider.
> >
> > With this added, the system can attempt to adjust the parent rate
> > when the proper flags are set which can lead to a more precise clock
> > value.
> >
> > On the imx8mplus, no clock changes are present.
> > On the Mini and Nano, this can help achieve more accurate
> > lcdif clocks. When trying to get a pixel clock of 31.500MHz
> > on an imx8m Nano, the clocks divided the 594MHz down, but
> > left the parent rate untouched which caused a calulation error.
> >
> > Before:
> > video_pll              594000000
> >   video_pll_bypass     594000000
> >     video_pll_out      594000000
> >       disp_pixel       31263158
> >         disp_pixel_clk 31263158
> >
> > Variance =3D -236842 Hz
> >
> > After this patch:
> > video_pll               31500000
> >   video_pll_bypass      31500000
> >     video_pll_out       31500000
> >       disp_pixel        31500000
> >         disp_pixel_clk  31500000
> >
> > Variance =3D 0 Hz
> >
> > All other clocks rates and parent were the same.
> > Similar results on imx8mm were found.
> >
>
> Peng / Abel,
>
> I was curious if either of you might have time to review this attempt
> at enabling determine_rate on the 8m's.  I tested this on the 8mm,
> 8mn, and 8mp, and found no regressions.

Gentle nudge.

It's been several weeks since the initial post and the DSI driver is
now available for Mini and Nano, so having this in Mini and Nano will
really help it sync various video sources.

thanks,

adam

>
> adam
> > Fixes: 690dccc4a0bf ("Revert "clk: imx: composite-8m: Add support to de=
termine_rate"")
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> > ---
> > V2:  Fix build warning found by build bot and fix prediv_value
> >      and div_value because the values stored are the divisor - 1,
> >      so we need to add 1 to the values to be correct.
> >
> > diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-c=
omposite-8m.c
> > index cbf0d7955a00..7a6e3ce97133 100644
> > --- a/drivers/clk/imx/clk-composite-8m.c
> > +++ b/drivers/clk/imx/clk-composite-8m.c
> > @@ -119,10 +119,41 @@ static int imx8m_clk_composite_divider_set_rate(s=
truct clk_hw *hw,
> >         return ret;
> >  }
> >
> > +static int imx8m_divider_determine_rate(struct clk_hw *hw,
> > +                                     struct clk_rate_request *req)
> > +{
> > +       struct clk_divider *divider =3D to_clk_divider(hw);
> > +       int prediv_value;
> > +       int div_value;
> > +
> > +       /* if read only, just return current value */
> > +       if (divider->flags & CLK_DIVIDER_READ_ONLY) {
> > +               u32 val;
> > +
> > +               val =3D readl(divider->reg);
> > +               prediv_value =3D val >> divider->shift;
> > +               prediv_value &=3D clk_div_mask(divider->width);
> > +               prediv_value++;
> > +
> > +               div_value =3D val >> PCG_DIV_SHIFT;
> > +               div_value &=3D clk_div_mask(PCG_DIV_WIDTH);
> > +               div_value++;
> > +
> > +               return divider_ro_determine_rate(hw, req, divider->tabl=
e,
> > +                                                PCG_PREDIV_WIDTH + PCG=
_DIV_WIDTH,
> > +                                                divider->flags, prediv=
_value * div_value);
> > +       }
> > +
> > +       return divider_determine_rate(hw, req, divider->table,
> > +                                     PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,
> > +                                     divider->flags);
> > +}
> > +
> >  static const struct clk_ops imx8m_clk_composite_divider_ops =3D {
> >         .recalc_rate =3D imx8m_clk_composite_divider_recalc_rate,
> >         .round_rate =3D imx8m_clk_composite_divider_round_rate,
> >         .set_rate =3D imx8m_clk_composite_divider_set_rate,
> > +       .determine_rate =3D imx8m_divider_determine_rate,
> >  };
> >
> >  static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
> > --
> > 2.39.2
> >