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References: <20230518184541.2627-10-jszhang@kernel.org> <mhng-e1d500da-688e-49bf-a2d8-bef0e2df48f8@palmer-ri-x1c9a>
In-Reply-To: <mhng-e1d500da-688e-49bf-a2d8-bef0e2df48f8@palmer-ri-x1c9a>
From:   Guo Ren <guoren@kernel.org>
Date:   Sat, 20 May 2023 09:16:24 +0800
Message-ID: <CAJF2gTQrfGyitzi7yhcs1dedG9NH2wnieoLu78SUNSaRiyL9dg@mail.gmail.com>
Subject: Re: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC
To:     Palmer Dabbelt <palmer@dabbelt.com>
Cc:     jszhang@kernel.org, tglx@linutronix.de,
        Marc Zyngier <maz@kernel.org>, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        Paul Walmsley <paul.walmsley@sifive.com>,
        aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        frank.li@vivo.com, wefu@redhat.com, uwu@icenowy.me
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Acked-by: Guo Ren <guoren@kernel.org>

On Sat, May 20, 2023 at 4:56=E2=80=AFAM Palmer Dabbelt <palmer@dabbelt.com>=
 wrote:
>
> On Thu, 18 May 2023 11:45:41 PDT (-0700), jszhang@kernel.org wrote:
> > Enable T-HEAD SoC config in defconfig to allow the default
> > upstream kernel to boot on Sipeed Lichee Pi 4A board.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/configs/defconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfi=
g
> > index d98d6e90b2b8..109e4b5b003c 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -27,6 +27,7 @@ CONFIG_EXPERT=3Dy
> >  CONFIG_PROFILING=3Dy
> >  CONFIG_SOC_MICROCHIP_POLARFIRE=3Dy
> >  CONFIG_ARCH_RENESAS=3Dy
> > +CONFIG_ARCH_THEAD=3Dy
> >  CONFIG_SOC_SIFIVE=3Dy
> >  CONFIG_SOC_STARFIVE=3Dy
> >  CONFIG_ARCH_SUNXI=3Dy
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>


--=20
Best Regards
 Guo Ren