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Date:   Sat, 20 May 2023 16:46:18 +0100
From:   Jonathan Cameron <jic23@kernel.org>
To:     =?UTF-8?B?0KHRgtCw0YDQuiDQk9C10L7RgNCz0LjQuSDQndC40LrQvtC70LDQtdCy0Lg=?=
         =?UTF-8?B?0Yc=?= <GNStark@sberdevices.ru>
Cc:     Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
        "lars@metafoo.de" <lars@metafoo.de>,
        "neil.armstrong@linaro.org" <neil.armstrong@linaro.org>,
        "khilman@baylibre.com" <khilman@baylibre.com>,
        "jbrunet@baylibre.com" <jbrunet@baylibre.com>,
        "andy.shevchenko@gmail.com" <andy.shevchenko@gmail.com>,
        "nuno.sa@analog.com" <nuno.sa@analog.com>,
        "linux-iio@vger.kernel.org" <linux-iio@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-amlogic@lists.infradead.org" 
        <linux-amlogic@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        kernel <kernel@sberdevices.ru>
Subject: Re: [PATCH v1] meson saradc: fix clock divider mask length
Message-ID: <20230520164618.08f26fd9@jic23-huawei>
In-Reply-To: <f0966e95-43c7-e6f6-8aeb-05f27691cec3@sberdevices.ru>
References: <20230515210545.2100161-1-gnstark@sberdevices.ru>
        <CAFBinCCc+t7Ks6fqz38cVrufPRFdxFgC9Qp+JhcM1KfD6pupTg@mail.gmail.com>
        <f0966e95-43c7-e6f6-8aeb-05f27691cec3@sberdevices.ru>
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On Wed, 17 May 2023 16:47:59 +0000
=D0=A1=D1=82=D0=B0=D1=80=D0=BA =D0=93=D0=B5=D0=BE=D1=80=D0=B3=D0=B8=D0=B9 =
=D0=9D=D0=B8=D0=BA=D0=BE=D0=BB=D0=B0=D0=B5=D0=B2=D0=B8=D1=87 <GNStark@sberd=
evices.ru> wrote:

> On 5/16/23 22:08, Martin Blumenstingl wrote:
> > Hi George,
> >
> > thank you for this patch!
> >
> > On Mon, May 15, 2023 at 11:06=E2=80=AFPM George Stark <gnstark@sberdevi=
ces.ru> wrote: =20
> >> From: George Stark <GNStark@sberdevices.ru>
> >>
> >> According to datasheets of supported meson SOCs
> >> length of ADC_CLK_DIV field is 6 bits long =20
> > I have a question about this sentence which doesn't affect this patch
> > - it's only about managing expectations:
> > Which SoC are you referring to?
> > This divider is only relevant on older SoCs that predate GXBB (S905).
> > To my knowledge all SoCs from GXBB onwards place the divider in the
> > main or AO clock controller, so this bitmask is irrelevant there. =20
>=20
> Hello Martin
>=20
> I've checked datasheets of all chips listed in meson_sar_adc_of_match arr=
ay in meson_saradc.c and everywhere this field is 6 bits long. According to=
 driver code and existing dts files this patch affects all supported chips =
except meson8.

On that note, do we want to add any clarifying text on the scope to the
commit message?

Jonathan

>=20
> Best regards
> George
>=20
>=20
> >> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in =
Amlogic Meson SoCs")
> >> Signed-off-by: George Stark <GNStark@sberdevices.ru> =20
> > Since my question above doesn't affect this patch:
> > Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > =20
>=20