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[2003:c7:8700:c900:cb50:4b66:2390:cd6b]) by smtp.gmail.com with ESMTPSA id ba7-20020a0564021ac700b0050daa883545sm1065889edb.64.2023.05.20.12.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 12:09:18 -0700 (PDT) From: Boerge Struempfel Cc: boerge.struempfel@gmail.com, bstruempfel@ultratronik.de, andy.shevchenko@gmail.com, festevam@gmail.com, amit.kumar-mahapatra@amd.com, broonie@kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 0/4] spi: add SPI_MOSI_IDLE_LOW mode bit Date: Sat, 20 May 2023 21:08:51 +0200 Message-Id: <20230520190856.34720-1-boerge.struempfel@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some spi controller switch the mosi line to high, whenever they are idle. This may not be desired in all use cases. For example neopixel leds can get confused and flicker due to misinterpreting the idle state. Therefore, we introduce a new spi-mode bit, with which the idle behaviour can be overwritten on a per device basis. --- Link for versions: v1 and v2: https://lore.kernel.org/linux-spi/20230511135632.78344-1-bstruempfel@ultratronik.de/ v3: https://lore.kernel.org/linux-spi/20230517103007.26287-1-boerge.struempfel@gmail.com/T/#t v4: https://lore.kernel.org/linux-spi/CAEktqctboF3=ykVNtPsifcmHzF6dWwoEcVh+O4H1u-R=TT6gHg@mail.gmail.com/T/#t Changes from V4: - Added the SPI_3WIRE_HIZ mode bit to spidev - Added the SPI_MOSI_IDLE_LOW mode bit to the spidev_test userspace tool and added the two other missing spi mode bits (SPI_3WIRE_HIZ and SPI_RX_CPHA_FLIP) to it as well. Changes from V3: - Added missing paranthesis which caused builderrors Changes from V2: - Removed the device-tree binding since this should not be managed by the DT but by the device itself. - Replaced all occurences of spi->chip_select with the corresponding macro spi_get_chipselect(spi,0) Changes from V1: - Added patch, introducing the new devicetree binding flag - Split the generic spi part of the patch from the imx-spi specific part - Replaced SPI_CPOL and SPI_CPHA by the combined SPI_MODE_X_MASK bit in the imx-spi.c modebits. - Added the SPI_MOSI_IDLE_LOW bit to spidev Boerge Struempfel (4): spi: add SPI_MOSI_IDLE_LOW mode bit spi: spi-imx: add support for SPI_MOSI_IDLE_LOW mode bit spi: spidev: add two new spi mode bits spi: spidev_test Add three missing spi mode bits drivers/spi/spi-imx.c | 9 +++- drivers/spi/spidev.c | 3 +- include/uapi/linux/spi/spi.h | 3 +- tools/spi/spidev_test.c | 101 ++++++++++++++++++++--------------- 4 files changed, 70 insertions(+), 46 deletions(-) -- 2.25.1