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From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Sun, 21 May 2023 11:53:19 +0300
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Subject: Re: [PATCH v1] meson saradc: fix clock divider mask length
To:     Jonathan Cameron <jic23@kernel.org>
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On Sat, May 20, 2023 at 6:30=E2=80=AFPM Jonathan Cameron <jic23@kernel.org>=
 wrote:
> On Wed, 17 May 2023 16:47:59 +0000
> =D0=A1=D1=82=D0=B0=D1=80=D0=BA =D0=93=D0=B5=D0=BE=D1=80=D0=B3=D0=B8=D0=B9=
 =D0=9D=D0=B8=D0=BA=D0=BE=D0=BB=D0=B0=D0=B5=D0=B2=D0=B8=D1=87 <GNStark@sber=
devices.ru> wrote:
> > On 5/16/23 22:08, Martin Blumenstingl wrote:

...

> > I've checked datasheets of all chips listed in meson_sar_adc_of_match a=
rray in meson_saradc.c and everywhere this field is 6 bits long. According =
to driver code and existing dts files this patch affects all supported chip=
s except meson8.
>
> On that note, do we want to add any clarifying text on the scope to the
> commit message?

We should, I think, but according to Martin's message, as I may
interpret it, the datasheet may also be wrong and some experiments on
a real hardware should prepend any change in the code.


--=20
With Best Regards,
Andy Shevchenko