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Date:   Sun, 21 May 2023 18:08:52 +0200
From:   David Epping <david.epping@missinglinkelectronics.com>
To:     Vladimir Oltean <olteanv@gmail.com>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        "David S . Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org, UNGLinuxDriver@microchip.com
Subject: Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock
Message-ID: <20230521160852.GB2208@nucnuc.mle>
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On Sun, May 21, 2023 at 04:12:26PM +0300, Vladimir Oltean wrote:
> Ah, no, I think the explanation is much simpler. I see the datasheet
> mentions that "RX_CLK output disable" is a sticky bit, which means it
> preserves its value across a reset.
> 
> In my case, it is the U-Boot driver which clears that setting, as part
> of configuring RGMII delays.
> https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/net/phy/mscc.c#L1553

Thanks for investigating and checking on your hardware.
Yes, my U-Boot does not support VSC850x yet, so Linux is the first
touching the registers.
For completeness: My PHY address is 0.