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Date:   Mon, 22 May 2023 18:17:44 +0800
From:   Xu Yilun <yilun.xu@intel.com>
To:     Nava kishore Manne <nava.kishore.manne@amd.com>
Cc:     mdf@kernel.org, hao.wu@intel.com, trix@redhat.com,
        michal.simek@amd.com, linux-fpga@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Alfonso Rodriguez <alfonso.rodriguezm@upm.es>
Subject: Re: [PATCH] fpga: zynq-fpga: Ensure proper xCAP interface switch
Message-ID: <ZGtBSGpPX3tK6mWY@yilunxu-OptiPlex-7050>
References: <20230519103232.3009096-1-nava.kishore.manne@amd.com>
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On 2023-05-19 at 16:02:32 +0530, Nava kishore Manne wrote:
> From: Alfonso Rodriguez <alfonso.rodriguezm@upm.es>
> 
> Ensure that the low-level fpga-manager driver for Zynq-7000 devices
> switches between reconfiguration interfaces as specified in the TRM
> (section 6.5.1: "Ensure that all outstanding transactions are completed
> before changing interfaces"); device (re)configuration may fail otherwise

Please briefly describe how the change conforms to the Doc in changelog,
rather than just leave the Doc for reviewers.

And please provide the Link to documentation.

> 
> Signed-off-by: Alfonso Rodriguez <alfonso.rodriguezm@upm.es>
> Tested-by: Nava kishore Manne <nava.kishore.manne@amd.com>

Please add your own SOB as you are handling the patch.

Thanks,
Yilun

> ---
>  drivers/fpga/zynq-fpga.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index ae0da361e6c6..88db9ac36887 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -493,15 +493,16 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
>  	if (err)
>  		return err;
>  
> -	/* Release 'PR' control back to the ICAP */
> -	zynq_fpga_write(priv, CTRL_OFFSET,
> -		zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
> -
>  	err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
>  				     intr_status & IXR_PCFG_DONE_MASK,
>  				     INIT_POLL_DELAY,
>  				     INIT_POLL_TIMEOUT);
>  
> +	/* Release 'PR' control back to the ICAP */
> +	zynq_fpga_write(priv, CTRL_OFFSET,
> +			zynq_fpga_read(priv, CTRL_OFFSET)
> +			& ~CTRL_PCAP_PR_MASK);
> +
>  	clk_disable(priv->clk);
>  
>  	if (err)
> -- 
> 2.25.1
>