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Date:   Mon, 22 May 2023 12:54:01 +0300
From:   Vladimir Oltean <olteanv@gmail.com>
To:     David Epping <david.epping@missinglinkelectronics.com>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        "David S . Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org, UNGLinuxDriver@microchip.com
Subject: Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock
Message-ID: <20230522095401.szzugrjohnwyqffk@skbuf>
References: <20230520160603.32458-1-david.epping@missinglinkelectronics.com>
 <20230520160603.32458-4-david.epping@missinglinkelectronics.com>
 <20230521134356.ar3itavhdypnvasc@skbuf>
 <20230521161650.GC2208@nucnuc.mle>
 <20230522094944.uylvgoepcmwjq5yj@skbuf>
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On Mon, May 22, 2023 at 12:49:44PM +0300, Vladimir Oltean wrote:
> Well, to be clear, I was suggesting:
> 
> /* Set the RGMII RX and TX clock skews individually, according to the PHY
>  * interface type, to:
>  *  * 0.2 ns (their default, and lowest, hardware value) if delays should
>  *    not be enabled
>  *  * 2.0 ns (which causes the data to be sampled at exactly half way between
>  *    clock transitions at 1000 Mbps) if delays should be enabled
>  */
> static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl,
> 				   u16 rgmii_rx_delay_mask,
> 				   u16 rgmii_tx_delay_mask)
> {
> 	u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
> 	u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
> 	u16 mask = rgmii_rx_delay_mask | rgmii_tx_delay_mask;
> 	u16 reg_val = 0;
> 	int rc;

Or rather:

	u16 mask = 0;

	if (phy_interface_is_rgmii(phydev))
		mask |= rgmii_rx_delay_mask | rgmii_tx_delay_mask;

	if (rgmii_cntl == VSC8502_RGMII_CNTL)
		mask |= VSC8502_RGMII_RX_CLK_DISABLE;

> 
> 	/* For traffic to pass, the VSC8502 family needs the RX_CLK disable bit
> 	 * to be unset for all PHY modes, so do that as part of the paged
> 	 * register modification.
> 	 */
> 	if (rgmii_cntl == VSC8502_RGMII_CNTL)
> 		mask |= VSC8502_RGMII_RX_CLK_DISABLE;
> 
> 	mutex_lock(&phydev->lock);
> 
> 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
> 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
> 		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;
> 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
> 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
> 		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
> 
> 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
> 			      rgmii_cntl, mask, reg_val);
> 
> 	mutex_unlock(&phydev->lock);
> 
> 	return rc;
> }