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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v5-20020a170902b7c500b001a6ade4c8c2si4398681plz.142.2023.05.22.04.51.04; Mon, 22 May 2023 04:51:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=TqhCXrO9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230400AbjEVLaM (ORCPT + 99 others); Mon, 22 May 2023 07:30:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229723AbjEVLaA (ORCPT ); Mon, 22 May 2023 07:30:00 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 370B98F for ; Mon, 22 May 2023 04:29:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684754998; x=1716290998; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version:content-transfer-encoding; bh=2vE1vxkZ/yDG2sKIbrPGCWDmnck+2hrLFnlbeMqrGW4=; b=TqhCXrO9ac+0iVhyASGxBMB9W98nUnod0mBO8lva68Y6FnoEyNZIvOy+ IvnxMWrOo6gEJW+8o14sho3EXk72VOp+Lr0eJnv5TsRAm5A7EfOQ7apx9 P6RgKLC5kVcoTIl+OirifPKK5whaYZhBji6EtIThK1sCIU/jexwnyFvLH XQbDqaK7+PcssE4Q89q/KGIheD+TB+OFkNO7VnzA7o2LuOEpzGocKx7nb F7hOOi4Hp1J2EsWaDkwOUIVxKVxFtK3y6ScBDsqlm70EQjZsleFeEly3l ZPQUauhgpOj350XaGyYtk1Bsp9dkeXxMk6kYL3o6Y3eFoS8zTMIX7NvaL A==; X-IronPort-AV: E=McAfee;i="6600,9927,10717"; a="416356596" X-IronPort-AV: E=Sophos;i="6.00,184,1681196400"; d="scan'208";a="416356596" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2023 04:29:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10717"; a="703467971" X-IronPort-AV: E=Sophos;i="6.00,184,1681196400"; d="scan'208";a="703467971" Received: from andreipo-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.54.228]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2023 04:29:54 -0700 From: Jani Nikula To: Sui Jingfeng <15330273260@189.cn>, David Laight , Sui Jingfeng , Li Yi Cc: Thomas Zimmermann , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "loongson-kernel@lists.loongnix.cn" Subject: Re: [PATCH] drm/drm_vblank.c: avoid unsigned int to signed int cast In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20230516173026.2990705-1-15330273260@189.cn> Date: Mon, 22 May 2023 14:29:52 +0300 Message-ID: <871qj8ob7z.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 18 May 2023, Sui Jingfeng <15330273260@189.cn> wrote: > On 2023/5/17 18:59, David Laight wrote: >> From: 15330273260@189.cn >>> Sent: 16 May 2023 18:30 >>> >>> From: Sui Jingfeng >>> >>> Both mode->crtc_htotal and mode->crtc_vtotal are u16 type, >>> mode->crtc_htotal * mode->crtc_vtotal will results a unsigned type. >> Nope, u16 gets promoted to 'signed int' and the result of the >> multiply is also signed. > > I believe that signed or unsigned is dependent on the declaration. > > I am talk about the math, while you are talking about compiler. > > I admit that u16 gets promoted to 'signed int' is true, but this is=20 > irrelevant, > > the point is how to understand the returned value. > > > How does the compiler generate the code is one thing, how do we=20 > interpret the result is another > > How does the compiler generate the code is NOT determined by us, while=20 > how do we interpret the result is determined by us. > > > I believe that using a u32 type to interpret the result(u16 * u16) is=20 > always true, it is true in the perspective of *math*. > > Integer promotions is the details of C program language. If the result=20 > of the multiply is signed, then there are risks that > > the result is negative, what's the benefit to present this risk to the=20 > programmer? > > What's the benefit to tell me(and others) that u16 * u16 yield a signed=20 > value? and can be negative? > > Using int type as the return type bring concerns to the programmer and=20 > the user of the function, > > even though this is not impossible in practice. In general, do not use unsigned types in arithmethic to avoid negative values, because most people will be tripped over by integer promotion rules, and you'll get negative values anyway. I'll bet most people will be surprised to see what this prints: #include #include int main(void) { uint16_t x =3D 0xffff; uint16_t y =3D 0xffff; uint64_t z =3D x * y; printf("0x%016lx\n", z); printf("%ld\n", z); printf("%d\n", x * y); } And it's not that different from what you have below. Your patch doesn't change anything, and doesn't make it any less confusing. BR, Jani. > >>> Using a u32 is enough to store the result, but considering that the >>> result will be casted to u64 soon after. We use a u64 type directly. >>> So there no need to cast it to signed type and cast back then. >> .... >>> - int frame_size =3D mode->crtc_htotal * mode->crtc_vtotal; >>> + u64 frame_size =3D mode->crtc_htotal * mode->crtc_vtotal; >> ... >>> - framedur_ns =3D div_u64((u64) frame_size * 1000000, dotclock); >>> + framedur_ns =3D div_u64(frame_size * 1000000, dotclock); >> The (u64) cast is there to extend the value to 64bits, not >> because the original type is signed. > > Sorry about my expression, I think my sentence did not mention anything=20 > about 'because the original type is signed'. > > In the contrary, my patch eliminated the concerns to the reviewer. It=20 > say that the results of the multiply can't be negative. > > My intent is to tell the compiler we want a unsigned return type, but=20 > GCC emit 'imul' instruction for the multiply...... > > I'm using u64 as the return type, because div_u64() function accept a=20 > u64 type value as its first argument. > >> The compiler will detect that the old code is a 32x32 multiply >> where a 64bit result is needed, that may not be true for the >> changed code (it would need to track back as far as the u16s). > > I don't believe my code could be wrong. > > when you use the word 'may', you are saying that it could be wrong after= =20 > apply my patch. > > Then you have to find at least one test example to prove you point, in=20 > which case my codes generate wrong results. > > Again I don't believe you could find one. > >> It is not uncommon to force a 64bit result from a multiply >> by making the constant 64bit. As in: >> div_u64(frame_size * 1000000ULL, dotclock); > > In fact, After apply this patch, the ASM code generated is same with befo= re. > > This may because the GCC is smart enough to generate optimized code in=20 > either case, > > I think It could be different with a different optimization-level. > > I have tested this patch on three different architecture,=C2=A0 I can not= =20 > find error still. > > Below is the assembly extract on x86-64: because GCC generate the same=20 > code in either case, > > so I pasted only one copy here. > > > 0000000000000530 : > =C2=A0=C2=A0=C2=A0=C2=A0 530:=C2=A0=C2=A0=C2=A0 f3 0f 1e fa=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 endbr64 > =C2=A0=C2=A0=C2=A0=C2=A0 534:=C2=A0=C2=A0=C2=A0 e8 00 00 00 00=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 callq=C2=A0 539=20 > > =C2=A0=C2=A0=C2=A0=C2=A0 539:=C2=A0=C2=A0=C2=A0 55=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 push=C2=A0=C2=A0 %rbp > =C2=A0=C2=A0=C2=A0=C2=A0 53a:=C2=A0=C2=A0=C2=A0 48 89 e5=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2= =A0 mov=C2=A0=C2=A0=C2=A0 %rsp,%rbp > =C2=A0=C2=A0=C2=A0=C2=A0 53d:=C2=A0=C2=A0=C2=A0 41 57=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = =C2=A0=C2=A0=C2=A0 push=C2=A0=C2=A0 %r15 > =C2=A0=C2=A0=C2=A0=C2=A0 53f:=C2=A0=C2=A0=C2=A0 41 56=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = =C2=A0=C2=A0=C2=A0 push=C2=A0=C2=A0 %r14 > =C2=A0=C2=A0=C2=A0=C2=A0 541:=C2=A0=C2=A0=C2=A0 41 55=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = =C2=A0=C2=A0=C2=A0 push=C2=A0=C2=A0 %r13 > =C2=A0=C2=A0=C2=A0=C2=A0 543:=C2=A0=C2=A0=C2=A0 41 54=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = =C2=A0=C2=A0=C2=A0 push=C2=A0=C2=A0 %r12 > =C2=A0=C2=A0=C2=A0=C2=A0 545:=C2=A0=C2=A0=C2=A0 53=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 push=C2=A0=C2=A0 %rbx > =C2=A0=C2=A0=C2=A0=C2=A0 546:=C2=A0=C2=A0=C2=A0 48 83 ec 18=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 sub=C2=A0=C2= =A0=C2=A0 $0x18,%rsp > =C2=A0=C2=A0=C2=A0=C2=A0 54a:=C2=A0=C2=A0=C2=A0 4c 8b 3f=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2= =A0 mov=C2=A0=C2=A0=C2=A0 (%rdi),%r15 > =C2=A0=C2=A0=C2=A0=C2=A0 54d:=C2=A0=C2=A0=C2=A0 41 8b 87 6c 01 00 00 =C2= =A0=C2=A0=C2=A0 mov=C2=A0=C2=A0=C2=A0 0x16c(%r15),%eax > =C2=A0=C2=A0=C2=A0=C2=A0 554:=C2=A0=C2=A0=C2=A0 85 c0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = =C2=A0=C2=A0=C2=A0 test=C2=A0=C2=A0 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