Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Mon, 22 May 2023 21:00:01 +0800
From:   Feng Tang <feng.tang@intel.com>
To:     Thomas Gleixner <tglx@linutronix.de>
CC:     Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        "Dave Hansen" <dave.hansen@intel.com>,
        "H . Peter Anvin" <hpa@zytor.com>,
        "Peter Zijlstra" <peterz@infradead.org>, <paulmck@kernel.org>,
        <rui.zhang@intel.com>, <x86@kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH RFC] x86/tsc: Make recalibration default on for
 TSC_KNOWN_FREQ cases
Message-ID: <ZGtnUQJy+1Nrazhy@feng-clx>
References: <20230522033018.1276836-1-feng.tang@intel.com>
 <87h6s4ye9b.ffs@tglx>
 <ZGssENXFKmOk/zL7@feng-clx>
 <87zg5wwppa.ffs@tglx>
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <87zg5wwppa.ffs@tglx>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?4hsVv6NjsC0kmIzYNoHjs9CQCSa8fLKXsjh9fhly+lf8x4dTzi1xcjILAfSp?=
 =?us-ascii?Q?tAFFPSxawTq7NdhBhGLbKLRj55noed++TXTTT6rkdYy73kSSjinbjBAcsPia?=
 =?us-ascii?Q?tJ5L7XW49q4OVPA75bqsd7ikWrI+JHLsBto44q7/qg5J5Hfrk30cJnomty9/?=
 =?us-ascii?Q?nAcW/buRSNiVStk+EAPZC+N6tk72YCOOCihbMcn8x7BIylP9cjuszDw2nUWL?=
 =?us-ascii?Q?D/im1Kf34awpAbHoxh2oF8vfLNIf/l1Vu151O0MkXXe8vuUqShaHJTZslcqV?=
 =?us-ascii?Q?lo4cuuD/+LX2j3ZFen3n/VtCx+r56z5E43QVIkyAGrhahQIYQlCOt5kw+V9v?=
 =?us-ascii?Q?wmHCDmAmwYrVvOMLPTiyyEZWuMAdkRhnfhIR90rfTDYeDOrDVz0V6iWSQiiF?=
 =?us-ascii?Q?fG2ZoNGByKU2V+qaIjBqfjCFb+B3G4KraOKuP+AvPgDPxLZkwWGzJkMqRE4d?=
 =?us-ascii?Q?qX6NbRQzAVsVYXt5YK9uNjYjE60p2TaA5EGH0eanq4BRjbjhrhbx/oynOfvr?=
 =?us-ascii?Q?w5GIzIrZsftield6BmSuw5i7NQDDb1k3zJadXFzQI6Nx9i3zTLHkKe4MTsrV?=
 =?us-ascii?Q?yIrcrqpQB3UBy8f/y5JlewCdniMJqXl/gfJBRc/2ZRL1q/EOFq+vC0SvRf0g?=
 =?us-ascii?Q?9/0pcqsLV3fbPF++UHQ1IJq18AlN6E+b8SKEGrfcGZ78h7cS2Djqtum/8KpN?=
 =?us-ascii?Q?GtZRQVZ0UQzrlQu5U6lBmH2/AhKyjgOacB8eP1gkST09QcdOtYASul2mPY/1?=
 =?us-ascii?Q?fOXtlmTgdDaCDvK3PZ4hZA2rmYhirP99K13Z9ArsYxq9J3hf2WhGoal5tQfM?=
 =?us-ascii?Q?WKXcSeudHPbsLuBF+N93Ma9+lqKY9wOW22Ahc1kr3lV64AO2BhLWfYCuEdv5?=
 =?us-ascii?Q?zBJnRGn72VWrlj9HsWEixoMQYfa1Q8MfIFX9ktVYJr0d29py3xo7F9gon9CF?=
 =?us-ascii?Q?fsTvyx8/GmZEZrJba/qf7f7rGSq5H8nWQB5VG1DiGTArJb44xUhzK0wpg1n4?=
 =?us-ascii?Q?cOOy9pR3T3SB5gMqO8UmOAYZ6TcafSIn3EcetUIcHvRQTrajl1qNqWcfrY6k?=
 =?us-ascii?Q?9C7sMP8Coo2YZtbZSvIuZ8GrQb/Q8RdW+5qGPeqqKYdSECWH30N+PUNTNhi6?=
 =?us-ascii?Q?IPALHBxu4PZnt/kixEMGL/TXgDTe8j8zhFuVb6fxWg/+kRJDUQCj6MuMNP/Q?=
 =?us-ascii?Q?2wjijypdDPi1SIizg7WMiSPbJ/2STebiVfLCexcls5JEUjRlRv/rFdKedJyO?=
 =?us-ascii?Q?GvqWpiGPO/r24M35RubZvJiji9gWV1/5awtt6zGYILUXkXQnSBHGZO5ZetwK?=
 =?us-ascii?Q?v0Tlj37DPnj0I71r3ZqS85co3ImV3O/GZ46GlTCLXSonBRp7Kck7n8c/v8DX?=
 =?us-ascii?Q?8jCWeOZxEiVFj2jCaHGg1K7AZFWq+lz29hbqTXpb4oe3jbpcOMifenxwDkWo?=
 =?us-ascii?Q?ntSxcd2nLysg1+uFk53HkXV9JFASeZSMxvK4mOPfeDVppKvLADEuSycGRinE?=
 =?us-ascii?Q?yYZDtGPScP031QLRd26RsWG62gwFuFO+V9OM+3yrhbrg+7xlkEeMn/LmzOel?=
 =?us-ascii?Q?BA8wBmITi3wDgAwSm2WRJ1mt41TP21w3Y/Yh8hy0?=
X-MS-Exchange-CrossTenant-Network-Message-Id: 59f8d747-3762-47fa-557c-08db5ac56ede
X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6304.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2023 13:07:02.0333
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: C4wWMO/sOk89qkWfrO6JLqkQMnf4vFGq+FDbUX5UZO/p8vmAlEmrNXOQwZdN0jPwmhxFY1MraaMdN9pNcHWhYw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR11MB7432
X-OriginatorOrg: intel.com
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
        DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,
        SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no
        version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, May 22, 2023 at 01:49:53PM +0200, Thomas Gleixner wrote:
> On Mon, May 22 2023 at 16:47, Feng Tang wrote:
> > On Mon, May 22, 2023 at 10:14:08AM +0200, Thomas Gleixner wrote:
> >> On Mon, May 22 2023 at 11:30, Feng Tang wrote:
> >> Are any of these affected platforms shipping already or is this just
> >> Intel internal muck?
> >
> > Paul and Rui can provide more info. AFAIK, those problems were raised
> > by external customers, so the platform were already shipped from
> > Intel. But I'm not sure they are commercial versions or early
> > engineering drops. 
> 
> So its at a company which knows how to update firmware, right?

Yes. And the recalibration may help to exposed the bug quickly.

> >> So why do you force this on everyone?
> >
> > How about we keep the optional parameter, and enforce the check for
> > bare metal platforms which got TSC frequency info from CPUID(0x15),
> > like:
> 
> What prevents a hypervisor from providing this info in CPUID(0x15)?
> 
> > @@ -670,8 +670,10 @@ unsigned long native_calibrate_tsc(void)
> >  	 * frequency and is the most accurate one so far we have. This
> >  	 * is considered a known frequency.
> >  	 */
> > -	if (crystal_khz != 0)
> > +	if (crystal_khz != 0) {
> >  		setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > +		tsc_force_recalibrate = 1;
> > +	}
> >  
> >  	/*
> >  	 * Some Intel SoCs like Skylake and Kabylake don't report the crystal
> 
> and five lines further down:
> 
> 	/*
> 	 * For Atom SoCs TSC is the only reliable clocksource.
> 	 * Mark TSC reliable so no watchdog on it.
> 	 */
> 	if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> 		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> 
> So its reliable and needs recalibration against hardware which does not
> exist.

I misunderstood it. When you said 'SOCs which lack legacy hardware',
I thought you were referring those old Merrifield/Medfield things,
which may have no HPET/ACPI PM_Timer but an APB timer, and mainly go
through MSR way (tsc_msr.c) for TSC frequency.

In this native_calibrate_tsc(), which touches the INTEL_FAM6_ATOM_GOLDMONT
and INTEL_FAM6_ATOM_GOLDMONT_D, I dug out one Apollo Lake and one
Denverton platform (which comply to those GOLDMNOT model), and they
both have 'hpet' and 'acpi_pm' clocksource registered. 

Thanks,
Feng

> 
> Thanks,
> 
>        tglx