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Date:   Mon, 22 May 2023 17:22:21 +0200
From:   David Epping <david.epping@missinglinkelectronics.com>
To:     Vladimir Oltean <olteanv@gmail.com>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        "David S . Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org, UNGLinuxDriver@microchip.com
Subject: Re: [PATCH net 3/3] net: phy: mscc: enable VSC8501/2 RGMII RX clock
Message-ID: <20230522152221.GA21090@nucnuc.mle>
References: <20230520160603.32458-1-david.epping@missinglinkelectronics.com>
 <20230520160603.32458-4-david.epping@missinglinkelectronics.com>
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 <20230521161650.GC2208@nucnuc.mle>
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 <20230522140057.GB18381@nucnuc.mle>
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On Mon, May 22, 2023 at 06:11:04PM +0300, Vladimir Oltean wrote:
> On Mon, May 22, 2023 at 04:00:57PM +0200, David Epping wrote:
> > Since the clock enablement now happens in all modes the existing rgmii
> > function name seems misleading to me.
> 
> To be fair, it's only as misleading as the datasheet name for the register
> that holds this field, "RGMII CONTROL". Anyway, the function could be
> renamed as necessary to be less confusing: vsc85xx_update_rgmii_ctrl()
> or something along those lines.
> 
> MDIO reads and writes are not exactly the quickest I/O in the world, and
> having 2 read-modify-write consecutive accesses to the same paged
> register (which in turn implies indirect access) just because readability
> seems like the type of thing that can play its part in deteriorating
> boot time latency. Maybe we can deal with the readability some other way.

You are right. It's an easy job for the CPU and saves time for
hardware access. I'll prepare and send a new patch set.

> > Also we don't want to enable for
> > all PHY types, and the differentiation is already available at the
> > caller. I would thus opt for a separate function and fewer conditional
> > statements.
> 
> I don't understand this. We don't? For what PHY types don't we want to
> enable the RX_CLK?

I meant all PHYs using vsc85xx_rgmii_set_skews() via vsc8584_config_init().
As you pointed out they don't have a clear definition of what bit 11 means
for them.
But we can easily differentiate using the condition you suggested.
I'll do that for the new patch version.