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[98.179.76.75]) by smtp.gmail.com with ESMTPSA id pp8-20020a056214138800b0061b62c15351sm2361791qvb.90.2023.05.22.17.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 17:17:15 -0700 (PDT) From: jsnitsel@redhat.com Date: Mon, 22 May 2023 17:17:13 -0700 To: Suravee Suthikulpanit Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, joro@8bytes.org, joao.m.martins@oracle.com, alejandro.j.jimenez@oracle.com, boris.ostrovsky@oracle.com, jon.grimm@amd.com, santosh.shukla@amd.com, vasant.hegde@amd.com, kishon.vijayabraham@amd.com Subject: Re: [PATCH v2 4/5] iommu/amd: Do not Invalidate IRT when disable IRTE caching Message-ID: \From: Jerry Snitselaar References: <20230519005529.28171-1-suravee.suthikulpanit@amd.com> <20230519005529.28171-5-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230519005529.28171-5-suravee.suthikulpanit@amd.com> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 18, 2023 at 08:55:28PM -0400, Suravee Suthikulpanit wrote: > With the Interrupt Remapping Table cache disabled, there is no need to > issue invalidate IRT and wait for its completion. Therefore, add logic > to bypass the operation. > > Suggested-by: Joao Martins > Signed-off-by: Suravee Suthikulpanit Would it be clearer for the summary to be "iommu/amd: Do not Invalidate IRT when IRTE caching is disabled"? Reviewed-by: Jerry Snitselaar > --- > drivers/iommu/amd/iommu.c | 21 +++++++++++++++------ > 1 file changed, 15 insertions(+), 6 deletions(-) > > diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c > index 0c4a2796bb0a..51c2b018433d 100644 > --- a/drivers/iommu/amd/iommu.c > +++ b/drivers/iommu/amd/iommu.c > @@ -1273,12 +1273,24 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) > u32 devid; > u16 last_bdf = iommu->pci_seg->last_bdf; > > + if (iommu->irtcachedis_enabled) > + return; > + > for (devid = 0; devid <= last_bdf; devid++) > iommu_flush_irt(iommu, devid); > > iommu_completion_wait(iommu); > } > > +static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid) > +{ > + if (iommu->irtcachedis_enabled) > + return; > + > + iommu_flush_irt(iommu, devid); > + iommu_completion_wait(iommu); > +} > + > void iommu_flush_all_caches(struct amd_iommu *iommu) > { > if (iommu_feature(iommu, FEATURE_IA)) { > @@ -3028,8 +3040,7 @@ static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, > > raw_spin_unlock_irqrestore(&table->lock, flags); > > - iommu_flush_irt(iommu, devid); > - iommu_completion_wait(iommu); > + iommu_flush_irt_and_complete(iommu, devid); > > return 0; > } > @@ -3048,8 +3059,7 @@ static int modify_irte(struct amd_iommu *iommu, > table->table[index] = irte->val; > raw_spin_unlock_irqrestore(&table->lock, flags); > > - iommu_flush_irt(iommu, devid); > - iommu_completion_wait(iommu); > + iommu_flush_irt_and_complete(iommu, devid); > > return 0; > } > @@ -3067,8 +3077,7 @@ static void free_irte(struct amd_iommu *iommu, u16 devid, int index) > iommu->irte_ops->clear_allocated(table, index); > raw_spin_unlock_irqrestore(&table->lock, flags); > > - iommu_flush_irt(iommu, devid); > - iommu_completion_wait(iommu); > + iommu_flush_irt_and_complete(iommu, devid); > } > > static void irte_prepare(void *entry, > -- > 2.31.1 >