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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n2-20020a170902d2c200b001ae3cb42bfdsi47592plc.634.2023.05.22.19.39.47; Mon, 22 May 2023 19:39:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233505AbjEWC2Z (ORCPT + 99 others); Mon, 22 May 2023 22:28:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229505AbjEWC2Y (ORCPT ); Mon, 22 May 2023 22:28:24 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4E146CA; Mon, 22 May 2023 19:28:23 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C5F3811FB; Mon, 22 May 2023 19:29:07 -0700 (PDT) Received: from [10.162.42.7] (unknown [10.162.42.7]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF45E3F67D; Mon, 22 May 2023 19:28:16 -0700 (PDT) Message-ID: Date: Tue, 23 May 2023 07:58:13 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH V3 3/6] coresight: etm4x: Drop pid argument from etm4_probe() Content-Language: en-US To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org Cc: Ganapatrao Kulkarni , Steve Clevenger , Rob Herring , Frank Rowand , Russell King , Greg Kroah-Hartman , "Rafael J. Wysocki" , Len Brown , Sudeep Holla , Lorenzo Pieralisi , Mathieu Poirier , Mike Leach , Leo Yan , devicetree@vger.kernel.org, linux-acpi@vger.kernel.org References: <20230519052149.1367814-1-anshuman.khandual@arm.com> <20230519052149.1367814-4-anshuman.khandual@arm.com> From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/19/23 18:08, Suzuki K Poulose wrote: > On 19/05/2023 06:21, Anshuman Khandual wrote: >> Coresight device pid can be retrieved from its iomem base address, which is >> stored in 'struct etm4x_drvdata'. This drops pid argument from etm4_probe() >> and 'struct etm4_init_arg'. Instead etm4_check_arch_features() derives the >> coresight device pid with a new helper coresight_get_pid(), right before it >> is consumed in etm4_hisi_match_pid(). >> >> Cc: Mathieu Poirier >> Cc: Suzuki K Poulose >> Cc: Mike Leach >> Cc: Leo Yan >> Cc: coresight@lists.linaro.org >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Anshuman Khandual >> --- >>   .../coresight/coresight-etm4x-core.c          | 29 ++++++++++--------- >>   include/linux/coresight.h                     | 12 ++++++++ >>   2 files changed, 27 insertions(+), 14 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 748d2ef53cb0..914ef6eb85d1 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -66,7 +66,6 @@ static u64 etm4_get_access_type(struct etmv4_config *config); >>   static enum cpuhp_state hp_online; >>     struct etm4_init_arg { >> -    unsigned int        pid; >>       struct device        *dev; >>       struct csdev_access    *csa; >>   }; >> @@ -370,9 +369,17 @@ static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) >>   } >>     static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, >> -                      unsigned int id) >> +                     struct csdev_access *csa) >>   { >> -    if (etm4_hisi_match_pid(id)) >> +    /* >> +     * coresight_get_pid() fetches device PID from the iomem >> +     * register based accesses, which cannot be performed on >> +     * system instruction based devices. >> +     */ > > Minor nit: Please fix the comment to say something like : > >     /* >      * TRCPIDR* registers are not required for ETMs with system >      * instructions. They must be identified by the MIDR+REVIDRs. >      * Skip the TRCPID checks for now. >      */ > > Rest looks good to me. Will change the in-code comment as suggested.