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[93.5.22.158]) by smtp.gmail.com with ESMTPSA id y21-20020a7bcd95000000b003f4e8530696sm11286717wmj.46.2023.05.23.03.58.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 May 2023 03:58:34 -0700 (PDT) Message-ID: Date: Tue, 23 May 2023 12:58:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 2/2] clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks Content-Language: en-US To: AngeloGioacchino Del Regno , mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, wenst@chromium.org, chun-jie.chen@mediatek.com, mandyjh.liu@mediatek.com, miles.chen@mediatek.com, zhaojh329@gmail.com, daniel@makrotopia.org, nfraprado@collabora.com, rex-bc.chen@mediatek.com, Garmin.Chang@mediatek.com, msp@baylibre.com, yangyingliang@huawei.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com References: <20230516135205.372951-1-angelogioacchino.delregno@collabora.com> <20230516135205.372951-3-angelogioacchino.delregno@collabora.com> From: Alexandre Mergnat In-Reply-To: <20230516135205.372951-3-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/05/2023 15:52, AngeloGioacchino Del Regno wrote: > Various MSDC core clocks, used for multiple MSDC controller instances, > share the same parent(s): in order to add parents selection in the > mtk-sd driver to achieve an accurate clock rate for all modes, remove > the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this > will make sure that a clk_set_rate() call performed for a clock on > a secondary controller will not change the rate of a common parent, > which would result in an overclock or underclock of one of the > controllers. > > Signed-off-by: AngeloGioacchino Del Regno > Reviewed-by: Matthias Brugger > Reviewed-by: Markus Schneider-Pargmann Tested on mt8365-evk board. Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat