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Date:   Tue, 23 May 2023 13:10:06 +0200
From:   Torsten Duwe <duwe@lst.de>
To:     Conor Dooley <conor.dooley@microchip.com>
Cc:     Xingyu Wu <xingyu.wu@starfivetech.com>,
        <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
        <yanhong.wang@starfivetech.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Conor Dooley <conor@kernel.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Rob Herring <robh+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        William Qiu <william.qiu@starfivetech.com>,
        <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL
 clock generator
Message-ID: <20230523131006.46997d84@blackhole.lan>
In-Reply-To: <20230523-fondue-monotype-0c751a8f0c13@wendy>
References: <20230512022036.97987-1-xingyu.wu@starfivetech.com>
        <20230512022036.97987-2-xingyu.wu@starfivetech.com>
        <20230519135733.GA10188@lst.de>
        <20230519-smokeless-guileless-2a71cae06509@wendy>
        <df43411e-8982-74f5-6148-e7281c37dada@starfivetech.com>
        <20230523-fondue-monotype-0c751a8f0c13@wendy>
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On Tue, 23 May 2023 09:28:39 +0100
Conor Dooley <conor.dooley@microchip.com> wrote:

> On Tue, May 23, 2023 at 10:56:43AM +0800, Xingyu Wu wrote:
> > On 2023/5/19 22:16, Conor Dooley wrote:
> > > On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote:
> > >> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote:
> > >> [...]

> > >> > +/* PLL clocks */
> > >> > +#define JH7110_CLK_PLL0_OUT			0
> > >> > +#define JH7110_CLK_PLL1_OUT			1
> > >> > +#define JH7110_CLK_PLL2_OUT			2
> > >> 
> > >> In U-Boot commit 58c9c60b Yanhong Wang added:
> > >> 
> > >> +
> > >> +#define JH7110_SYSCLK_PLL0_OUT                       190
> > >> +#define JH7110_SYSCLK_PLL1_OUT                       191
> > >> +#define JH7110_SYSCLK_PLL2_OUT                       192
> > >> +
> > >> +#define JH7110_SYSCLK_END                    193
[...]
> > > Ohh, that's not good.. If you pass the U-Boot dtb to Linux it
> > > won't understand the numbering. The headers are part of the
> > > dt-binding :/

In fact, the clock index >= 190 makes linux hang on boot, waiting with
EPROBE_DEFER for every device's clock, because the sysclk driver errors
out with EINVAL (jh7110_sysclk_get()).

> > Because PLL driver is separated from SYSCRG drivers in Linux, the
> > numbering starts from 0. But in Uboot, the PLL driver is included
> > in the SYSCRG driver, and the number follows the SYSCRG.
> 
> Unfortunately, how you choose to construct your drivers has nothing to
> do with this.
> These defines/numbers appear in the dts and are part of the DT ABI.
> The same dts is supposed to work for Linux & U-Boot.

The JH7110 has 6 blocks of 64k iomem in that functional area:
{SYS,STG,AON} x {CRG,SYSCON}. None of these has 190 clocks.
The good news: the current DTS, as proposed here and in U-Boot master,
provides nodes for all 6 entities. The bad news is that the clock
assignments to those nodes and their numbering is messed up.

AFAICT PLL{0,1,2} _are_ generated in SYS_SYSCON and thus U-Boot gets it
wrong, in addition to the erroneous DTS.

	Torsten