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Received: from DM6PR12MB4123.namprd12.prod.outlook.com (2603:10b6:5:21f::23) by BL0PR12MB4996.namprd12.prod.outlook.com (2603:10b6:208:1c6::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.15; Wed, 24 May 2023 06:56:31 +0000 Received: from DM6PR12MB4123.namprd12.prod.outlook.com ([fe80::8700:a051:2ddf:d350]) by DM6PR12MB4123.namprd12.prod.outlook.com ([fe80::8700:a051:2ddf:d350%4]) with mapi id 15.20.6433.015; Wed, 24 May 2023 06:56:30 +0000 Message-ID: <9d24f5ae-75e6-2358-f9bc-72414c5f250f@amd.com> Date: Wed, 24 May 2023 12:31:24 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH V2 2/9] ASoC: amd: ps: handle SoundWire interrupts in acp pci driver Content-Language: en-US To: Pierre-Louis Bossart , broonie@kernel.org Cc: alsa-devel@alsa-project.org, Basavaraj.Hiregoudar@amd.com, Sunil-kumar.Dommati@amd.com, Mastan.Katragadda@amd.com, Arungopal.kondaveeti@amd.com, mario.limonciello@amd.com, Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Syed Saba Kareem , open list References: <20230522133122.166841-1-Vijendar.Mukunda@amd.com> <20230522133122.166841-3-Vijendar.Mukunda@amd.com> <134a2efd-648a-fb4b-4b61-154173b97f04@linux.intel.com> <2e8d3af4-7d54-becf-1084-c9b07a3436d0@amd.com> From: "Mukunda,Vijendar" In-Reply-To: Content-Type: text/plain; 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>>>> struct pdm_dev_data *ps_pdm_data; >>>> - u32 val; >>>> + struct amd_sdw_manager *amd_manager; >>>> + u32 ext_intr_stat, ext_intr_stat1; >>>> + u16 irq_flag = 0; >>>> u16 pdev_index; >>>> >>>> adata = dev_id; >>>> if (!adata) >>>> return IRQ_NONE; >>>> + ext_intr_stat = readl(adata->acp63_base + ACP_EXTERNAL_INTR_STAT); >>>> + if (ext_intr_stat & ACP_SDW0_STAT) { >>>> + writel(ACP_SDW0_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT); >>> [1] >>> >>> this is confusing, if this is w1c, should this be: >>> >>> writel(ext_intr_stat, adata->acp63_base + ACP_EXTERNAL_INTR_STAT); >>> >>> Otherwise you may be clearing fields that have not been set? >> As per our register spec, writing zero to register fields doesn't >> have any effect. Only writing 1 to register bit will clear that >> interrupt. >> We are handling bit by bit irq check and clearing the irq mask >> based on irq bit and take an action related to that particular irq >> bit. > Right, maybe an explanation in the commit message would help. will update the commit message.