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Wed, 24 May 2023 12:43:12 +0000 Received: from DM4PR12MB5769.namprd12.prod.outlook.com ([fe80::2c4d:1cf:626a:370d]) by DM4PR12MB5769.namprd12.prod.outlook.com ([fe80::2c4d:1cf:626a:370d%7]) with mapi id 15.20.6433.015; Wed, 24 May 2023 12:43:12 +0000 From: Krishna Yarlagadda To: Mark Brown , Jarkko Sakkinen CC: Thierry Reding , "jsnitsel@redhat.com" , "robh+dt@kernel.org" , "peterhuewe@gmx.de" , "jgg@ziepe.ca" , "krzysztof.kozlowski+dt@linaro.org" , "linux-spi@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-integrity@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Jonathan Hunter , Sowjanya Komatineni , Laxman Dewangan Subject: RE: [Patch V10 2/3] tpm_tis-spi: Add hardware wait polling Thread-Topic: [Patch V10 2/3] tpm_tis-spi: Add hardware wait polling Thread-Index: AQHZdDGUn7qO3n0DaEywabZxmXB7Nq85AnkAgAFcuoCAAC9+AIAACQqAgAADlQCAGR6r0IAV1ZKg Date: Wed, 24 May 2023 12:43:12 +0000 Message-ID: References: <20230421091309.2672-1-kyarlagadda@nvidia.com> <20230421091309.2672-3-kyarlagadda@nvidia.com> <3df39f0b-70dc-4b42-bae1-72c07607cbc7@sirena.org.uk> <5fae29cd-d5f4-4616-be1c-1cd4d5b9a538@sirena.org.uk> In-Reply-To: Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5769.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 836e641e-1c06-4aee-a415-08db5c546fc9 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 May 2023 12:43:12.5502 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: FAtwtUYpOTjfP9WNYVOCxQ/5ZPQouwKZ+WnsrSO2keFdXweOJ0+KthvDEAyR3lfI9VJge59moddEDVN3E/Y+2g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7956 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Krishna Yarlagadda > Sent: Wednesday, May 10, 2023 8:41 PM > To: Thierry Reding ; Mark Brown > > Cc: Jarkko Sakkinen ; jsnitsel@redhat.com; > robh+dt@kernel.org; peterhuewe@gmx.de; jgg@ziepe.ca; > krzysztof.kozlowski+dt@linaro.org; linux-spi@vger.kernel.org; linux- > tegra@vger.kernel.org; linux-integrity@vger.kernel.org; linux- > kernel@vger.kernel.org; Jonathan Hunter ; > Sowjanya Komatineni ; Laxman Dewangan > > Subject: RE: [Patch V10 2/3] tpm_tis-spi: Add hardware wait polling >=20 >=20 > > -----Original Message----- > > From: Thierry Reding > > Sent: 24 April 2023 21:02 > > To: Mark Brown > > Cc: Jarkko Sakkinen ; Krishna Yarlagadda > > ; jsnitsel@redhat.com; robh+dt@kernel.org; > > peterhuewe@gmx.de; jgg@ziepe.ca; krzysztof.kozlowski+dt@linaro.org; > > linux-spi@vger.kernel.org; linux-tegra@vger.kernel.org; linux- > > integrity@vger.kernel.org; linux-kernel@vger.kernel.org; Jonathan Hunte= r > > ; Sowjanya Komatineni > > ; Laxman Dewangan > > Subject: Re: [Patch V10 2/3] tpm_tis-spi: Add hardware wait polling > > > > On Mon, Apr 24, 2023 at 04:18:45PM +0100, Mark Brown wrote: > > > On Mon, Apr 24, 2023 at 04:46:24PM +0200, Thierry Reding wrote: > > > > > > > Would it make sense for you to pick up patch 2/3 as well? As far as= I > > > > can tell there's a build dependency on patch 1/3 because of the new= ly > > > > added SPI_TPM_HW_FLOW symbol. > > > > > > I'll include it in my pull request for spi this time round so it shou= ld > > > end up in -rc1, my thinking was that I was happy with the SPI bits an= d > > > if it was in -rc1 then the TPM bits could be handled without cross tr= ee > > > issues when the review was sorted (which it is now but wasn't at the > > > time). If the SPI side doesn't make -rc1 for some reason I can pick = up > > > the TPM bit as well, and/or do a signed tag. > > > > Sounds good. > > > > Thanks, > > Thierry >=20 > Mark, > Now that SPI changes are in, can we pull this TPM change for rc2. > Will this be picked into SPI or TPM list? Jarkko, Mark, Can we pick this change in TPM list since SPI header changes are in. Regards KY > Thanks, > KY