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From:   Jim Mattson <jmattson@google.com>
Date:   Wed, 24 May 2023 14:32:44 -0700
Message-ID: <CALMp9eQrDX6=gJzybegjzDJ665NCuWmESt-sZrKHcncnuENdpA@mail.gmail.com>
Subject: Re: [PATCH 5/5] KVM: x86/pmu: Hide guest counter updates from the
 VMRUN instruction
To:     Sean Christopherson <seanjc@google.com>
Cc:     Sandipan Das <sandipan.das@amd.com>,
        Like Xu <like.xu.linux@gmail.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Ravi Bangoria <ravi.bangoria@amd.com>, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Santosh Shukla <santosh.shukla@amd.com>,
        "Tom Lendacky (AMD)" <thomas.lendacky@amd.com>,
        Ananth Narayan <ananth.narayan@amd.com>
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On Wed, May 24, 2023 at 2:29=E2=80=AFPM Sean Christopherson <seanjc@google.=
com> wrote:
>
> On Wed, May 24, 2023, Jim Mattson wrote:
> > On Wed, May 24, 2023 at 1:41=E2=80=AFPM Sean Christopherson <seanjc@goo=
gle.com> wrote:
> > >
> > > On Wed, Apr 26, 2023, Sandipan Das wrote:
> > > > Hi Sean, Like,
> > > >
> > > > On 4/19/2023 7:11 PM, Like Xu wrote:
> > > > >> Heh, it's very much explicable, it's just not desirable, and you=
 and I would argue
> > > > >> that it's also incorrect.
> > > > >
> > > > > This is completely inaccurate from the end guest pmu user's persp=
ective.
> > > > >
> > > > > I have a toy that looks like virtio-pmu, through which guest user=
s can get hypervisor performance data.
> > > > > But the side effect of letting the guest see the VMRUN instructio=
n by default is unacceptable, isn't it ?
> > > > >
> > > > >>
> > > > >> AMD folks, are there plans to document this as an erratum?=C3=AF=
=C2=BF=C2=BD I agree with Like that
> > > > >> counting VMRUN as a taken branch in guest context is a CPU bug, =
even if the behavior
> > > > >> is known/expected.
> > > > >
> > > >
> > > > This behaviour is architectural and an erratum will not be issued. =
However, for clarity, a future
> > > > release of the APM will include additional details like the followi=
ng:
> > > >
> > > >   1) From the perspective of performance monitoring counters, VMRUN=
s are considered as far control
> > > >      transfers and VMEXITs as exceptions.
> > > >
> > > >   2) When the performance monitoring counters are set up to count e=
vents only in certain modes
> > > >      through the "OsUserMode" and "HostGuestOnly" bits, instruction=
s and events that change the
> > > >      mode are counted in the target mode. For example, a SYSCALL fr=
om CPL 3 to CPL 0 with a
> > > >      counter set to count retired instructions with USR=3D1 and OS=
=3D0 will not cause an increment of
> > > >      the counter. However, the SYSRET back from CPL 0 to CPL 3 will=
 cause an increment of the
> > > >      counter and the total count will end up correct. Similarly, wh=
en counting PMCx0C6 (retired
> > > >      far control transfers, including exceptions and interrupts) wi=
th Guest=3D1 and Host=3D0, a VMRUN
> > > >      instruction will cause an increment of the counter. However, t=
he subsequent VMEXIT that occurs,
> > > >      since the target is in the host, will not cause an increment o=
f the counter and so the total
> > > >      count will end up correct.
> > >
> > > The count from the guest's perspective does not "end up correct".  Un=
like SYSCALL,
> > > where _userspace_ deliberately and synchronously executes a branch in=
struction,
> > > VMEXIT and VMRUN are supposed to be transparent to the guest and can =
be completely
> > > asynchronous with respect to guest code execution, e.g. if the host i=
s spamming
> > > IRQs, the guest will see a potentially large number of bogus (from it=
's perspective)
> > > branches retired.
> >
> > The reverse problem occurs when a PMC is configured to count "CPUID
> > instructions retired." Since KVM intercepts CPUID and emulates it, the
> > PMC will always read 0, even if the guest executes a tight loop of
> > CPUID instructions.
> >
> > The PMU is not virtualizable on AMD CPUs without significant
> > hypervisor corrections. I have to wonder if it's really worth the
> > effort.
>
> Per our offlist chat, my understanding is that there are caveats with vPM=
Us that
> it's simply not feasible for a hypervisor to handle.  I.e. virtualizing a=
ny x86
> PMU with 100% accuracy isn't happening anytime soon.
>
> The way forward is likely to evaluate each caveat on a case-by-case basis=
 to
> determine whether or not the cost of the fixup in KVM is worth the benefi=
t to
> the guest.  E.g. emulating "CPUID instructions retired" seems like it wou=
ld be
> fairly straightforward.  AFAICT, fixing up the VMRUN stuff is quite diffi=
cult though.

Yeah. The problem with fixing up "CPUID instructions retired" is
tracking what the event encoding is for every F/M/S out there. It's
not worth it.