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References: <ZGuDJos8D7N0J6Z2@francesco-nb.int.toradex.com> <ZG4ISE3WXlTM3H54@debian.me>
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From:   Johannes Pointner <h4nn35.work@gmail.com>
Date:   Thu, 25 May 2023 08:31:00 +0200
Message-ID: <CAHvQdo0gucr-GcWc9YFxsP4WwPUdK9GQ6w-5t9CuqqvPTv+VcA@mail.gmail.com>
Subject: Re: DP83867 ethernet PHY regression
To:     Francesco Dolcini <francesco@dolcini.it>,
        Bagas Sanjaya <bagasdotme@gmail.com>,
        Andrew Lunn <andrew@lunn.ch>,
        Praneeth Bajjuri <praneeth@ti.com>
Cc:     Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Grygorii Strashko <grygorii.strashko@ti.com>,
        Dan Murphy <dmurphy@ti.com>
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On Wed, May 24, 2023 at 3:22=E2=80=AFPM Bagas Sanjaya <bagasdotme@gmail.com=
> wrote:
>
> On Mon, May 22, 2023 at 04:58:46PM +0200, Francesco Dolcini wrote:
> > Hello all,
> > commit da9ef50f545f ("net: phy: dp83867: perform soft reset and retain
> > established link") introduces a regression on my TI AM62 based board.
> >
> > I have a working DTS with Linux TI 5.10 downstream kernel branch, while
> > testing the DTS with v6.4-rc in preparation of sending it to the mailin=
g
> > list I noticed that ethernet is working only on a cold poweron.
> >
> > With da9ef50f545f reverted it always works.
> >
> > Here the DTS snippet for reference:
> >
> > &cpsw_port1 {
> >       phy-handle =3D <&cpsw3g_phy0>;
> >       phy-mode =3D "rgmii-rxid";
> > };
> >
> > &cpsw3g_mdio {
> >       assigned-clocks =3D <&k3_clks 157 20>;
> >       assigned-clock-parents =3D <&k3_clks 157 22>;
> >       assigned-clock-rates =3D <25000000>;
> >
> >       cpsw3g_phy0: ethernet-phy@0 {
> >               compatible =3D "ethernet-phy-id2000.a231";
> >               reg =3D <0>;
> >               interrupt-parent =3D <&main_gpio0>;
> >               interrupts =3D <25 IRQ_TYPE_EDGE_FALLING>;
> >               reset-gpios =3D <&main_gpio0 17 GPIO_ACTIVE_LOW>;
> >               reset-assert-us =3D <10>;
> >               reset-deassert-us =3D <1000>;
> >               ti,fifo-depth =3D <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> >               ti,rx-internal-delay =3D <DP83867_RGMIIDCTL_2_00_NS>;
> >       };
> > };
> >
>
> Thanks for the regression report. I'm adding it to regzbot:
>
> #regzbot ^introduced: da9ef50f545f86
> #regzbot title: TI AM62 DTS regression due to dp83867 soft reset

Hello Francesco,

I had a similar issue with a patch like this, but in my case it was the DP8=
3822.
https://lore.kernel.org/netdev/CAHvQdo2yzJC89K74c_CZFjPydDQ5i22w36XPR5tKVv_=
W8a2vcg@mail.gmail.com/
I also raised the question for the commit da9ef50f545f.
https://lore.kernel.org/lkml/CAHvQdo1U_L=3DpETmTJXjdzO+k7vNTxMyujn99Y3Ot9xA=
yQu=3DatQ@mail.gmail.com/

The problem was/is for me that the phy gets the clock from the CPU and
the phy is already initialized in the u-boot.
During the Linux kernel boot up there is a short amount of time where
no clock is delivered to the phy.
The phy didn't like this and was most of the time not usable anymore.
The only thing that brought the phy/link back was resetting the phy
using the phytool.

Regards,
Hannes