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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e2-20020a636902000000b0051b13a071a8si584180pgc.575.2023.05.25.01.12.37; Thu, 25 May 2023 01:12:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=NxrV6Htj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234923AbjEYHuv (ORCPT + 99 others); Thu, 25 May 2023 03:50:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238061AbjEYHuY (ORCPT ); Thu, 25 May 2023 03:50:24 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6149D1BD; Thu, 25 May 2023 00:50:23 -0700 (PDT) X-UUID: cb5c95d2fad011ed9cb5633481061a41-20230525 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=YJSCef8WIl7T1XrVlzzSR6gNu60yYwDXceY/Q3jiTDg=; b=NxrV6Htjmk7HcLgnR8o8Rogzd7kH07Ccpnm8ZcWuzjadsokLf+Vui0xi0sDUpXiCrK7gmkiyPEfOIjngFdKISCHFQCZNBYl/6NGKEeYNxrLi7TZ8hgrtEGvDgZ/TMdo4cLKVIfUkDcsC/kGkdIkchap/Y1z4YSvYgoLdflFvwME=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.25,REQID:d747c175-03e7-4cef-8e7b-fba5fca30538,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:d5b0ae3,CLOUDID:7e05833c-7aa7-41f3-a6bd-0433bee822f3,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: cb5c95d2fad011ed9cb5633481061a41-20230525 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 200258964; Thu, 25 May 2023 15:50:19 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 25 May 2023 15:50:17 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 25 May 2023 15:50:17 +0800 From: Runyang Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: , , , , , Runyang Chen Subject: [PATCH v4 1/2] dt-bindings: reset: mt8188: add thermal reset control bit Date: Thu, 25 May 2023 15:50:10 +0800 Message-ID: <20230525075011.7032-2-runyang.chen@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20230525075011.7032-1-runyang.chen@mediatek.com> References: <20230525075011.7032-1-runyang.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To support reset of infra_ao, add the index of infra_ao reset of thermal for MT8188. Signed-off-by: Runyang Chen Acked-by: Conor Dooley --- include/dt-bindings/reset/mt8188-resets.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h index 377cdfda82a9..ba9a5e9b8899 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -33,4 +33,9 @@ #define MT8188_TOPRGU_SW_RST_NUM 24 +/* INFRA resets */ +#define MT8188_INFRA_RST1_THERMAL_MCU_RST 0 +#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 +#define MT8188_INFRA_RST3_PTP_CTRL_RST 2 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ -- 2.18.0