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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH v4 2/2] clk: mediatek: reset: add infra_ao reset support for MT8188 Content-Language: en-US To: Runyang Chen , Michael Turquette , Stephen Boyd , Matthias Brugger , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org References: <20230525075011.7032-1-runyang.chen@mediatek.com> <20230525075011.7032-3-runyang.chen@mediatek.com> From: AngeloGioacchino Del Regno In-Reply-To: <20230525075011.7032-3-runyang.chen@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Il 25/05/23 09:50, Runyang Chen ha scritto: > The infra_ao reset is needed for MT8188. > - Add mtk_clk_rst_desc for MT8188. > - Add register reset controller function for MT8188 infra_ao. > - Add infra_ao_idx_map for MT8188. > > Signed-off-by: Runyang Chen Reviewed-by: AngeloGioacchino Del Regno > Reported-by: kernel test robot > Closes: https://lore.kernel.org/oe-kbuild-all/202305242320.AZzmINEa-lkp@intel.com/ > --- > drivers/clk/mediatek/clk-mt8188-infra_ao.c | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/mediatek/clk-mt8188-infra_ao.c > index a38ddc7b6a88..f590178737cb 100644 > --- a/drivers/clk/mediatek/clk-mt8188-infra_ao.c > +++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c > @@ -5,6 +5,7 @@ > */ > > #include > +#include > #include > #include > > @@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] = { > "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), > }; > > +static u16 infra_ao_rst_ofs[] = { > + INFRA_RST0_SET_OFFSET, > + INFRA_RST1_SET_OFFSET, > + INFRA_RST2_SET_OFFSET, > + INFRA_RST3_SET_OFFSET, > + INFRA_RST4_SET_OFFSET, > +}; > + > +static u16 infra_ao_idx_map[] = { > + [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2, > + [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4, > + [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5, > +}; > + > +static const struct mtk_clk_rst_desc infra_ao_rst_desc = { > + .version = MTK_RST_SET_CLR, > + .rst_bank_ofs = infra_ao_rst_ofs, > + .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), > + .rst_idx_map = infra_ao_idx_map, > + .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), > +}; > + > static const struct mtk_clk_desc infra_ao_desc = { > .clks = infra_ao_clks, > .num_clks = ARRAY_SIZE(infra_ao_clks), > + .rst_desc = &infra_ao_rst_desc, > }; > > static const struct of_device_id of_match_clk_mt8188_infra_ao[] = {