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Date:   Thu, 25 May 2023 10:08:57 +0100
Message-ID: <86o7m8dbh2.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Bjorn Helgaas <helgaas@kernel.org>
Cc:     Huacai Chen <chenhuacai@loongson.cn>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        "Ahmed S . Darwish" <darwi@linutronix.de>,
        Jason Gunthorpe <jgg@ziepe.ca>,
        Kevin Tian <kevin.tian@intel.com>, linux-pci@vger.kernel.org,
        Jianmin Lv <lvjianmin@loongson.cn>,
        Huacai Chen <chenhuacai@gmail.com>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        loongson-kernel@lists.loongnix.cn,
        Juxin Gao <gaojuxin@loongson.cn>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] pci: irq: Add an early parameter to limit pci irq numbers
In-Reply-To: <ZG4rZYBKaWrsctuH@bhelgaas>
References: <20230524093623.3698134-1-chenhuacai@loongson.cn>
        <ZG4rZYBKaWrsctuH@bhelgaas>
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On Wed, 24 May 2023 16:21:09 +0100,
Bjorn Helgaas <helgaas@kernel.org> wrote:
> 
> [+cc Marc, LKML]
> 
> On Wed, May 24, 2023 at 05:36:23PM +0800, Huacai Chen wrote:
> > Some platforms (such as LoongArch) cannot provide enough irq numbers as
> > many as logical cpu numbers. So we should limit pci irq numbers when
> > allocate msi/msix vectors, otherwise some device drivers may fail at
> > initialization. This patch add a cmdline parameter "pci_irq_limit=xxxx"
> > to control the limit.
> > 
> > The default pci msi/msix number limit is defined 32 for LoongArch and
> > NR_IRQS for other platforms.
> 
> The IRQ experts can chime in on this, but this doesn't feel right to
> me.  I assume arch code should set things up so only valid IRQ numbers
> can be allocated.  This doesn't seem necessarily PCI-specific, I'd
> prefer to avoid an arch #ifdef here, and I'd also prefer to avoid a
> command-line parameter that users have to discover and supply.

I'd tend to agree. The irqchip driver that provides the interrupt
numbers should perform the capping, not the core PCI code.

Furthermore, MSI allocation is never guaranteed anyway, and drivers
shouldn't expect to get all the interrupts they request. If they do,
they need fixing.

Overall, interrupt architectures that provide as few as 32 possible
interrupts for MSIs will be crippled, and there isn't much we can do
about it. This also applies to a large number of ARM systems that use
the Designware IP.

	M.

-- 
Without deviation from the norm, progress is not possible.