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Thu, 25 May 2023 03:07:02 -0700 (PDT) X-Gm-Message-State: AC+VfDwx8Qdkk/J3VBXjIeO9TeWgzZn1xJtzm8w6m0r3oBe1ibJofYF0 i5k6ko9ZB3Zr+VP/PKTXs67Qp9slq5gZAzc2GG8= X-Received: by 2002:a17:907:3e29:b0:971:485:206 with SMTP id hp41-20020a1709073e2900b0097104850206mr1119430ejc.54.1685009220885; Thu, 25 May 2023 03:07:00 -0700 (PDT) MIME-Version: 1.0 References: <20230419062505.257231-1-leobras@redhat.com> In-Reply-To: From: Guo Ren Date: Thu, 25 May 2023 18:06:49 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 1/1] riscv/atomic.h: Deduplicate arch_atomic.* To: Leonardo Bras Soares Passos Cc: Will Deacon , Peter Zijlstra , Boqun Feng , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 25, 2023 at 5:31=E2=80=AFPM Leonardo Bras Soares Passos wrote: > > Friendly ping? > > On Wed, Apr 19, 2023 at 3:25=E2=80=AFAM Leonardo Bras wrote: > > > > Some functions use mostly the same asm for 32-bit and 64-bit versions. > > > > Make a macro that is generic enough and avoid code duplication. > > > > Signed-off-by: Leonardo Bras > > --- > > arch/riscv/include/asm/atomic.h | 164 +++++++++++++++----------------- > > 1 file changed, 76 insertions(+), 88 deletions(-) > > > > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/a= tomic.h > > index 0dfe9d857a762..85eb2edbc8219 100644 > > --- a/arch/riscv/include/asm/atomic.h > > +++ b/arch/riscv/include/asm/atomic.h > > @@ -196,22 +196,28 @@ ATOMIC_OPS(xor, xor, i) > > #undef ATOMIC_FETCH_OP > > #undef ATOMIC_OP_RETURN > > > > +#define _arch_atomic_fetch_add_unless(_prev, _rc, counter, _a, _u, sfx= ) \ > > +({ = \ > > + __asm__ __volatile__ ( = \ > > + "0: lr." sfx " %[p], %[c]\n" = \ > > + " beq %[p], %[u], 1f\n" = \ > > + " add %[rc], %[p], %[a]\n" = \ > > + " sc." sfx ".rl %[rc], %[rc], %[c]\n" = \ > > + " bnez %[rc], 0b\n" = \ > > + " fence rw, rw\n" = \ > > + "1:\n" = \ > > + : [p]"=3D&r" (_prev), [rc]"=3D&r" (_rc), [c]"+A" (count= er) \ > > + : [a]"r" (_a), [u]"r" (_u) = \ > > + : "memory"); = \ > > +}) > > + > > /* This is required to provide a full barrier on success. */ > > static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, i= nt a, int u) > > { > > int prev, rc; > > > > - __asm__ __volatile__ ( > > - "0: lr.w %[p], %[c]\n" > > - " beq %[p], %[u], 1f\n" > > - " add %[rc], %[p], %[a]\n" > > - " sc.w.rl %[rc], %[rc], %[c]\n" > > - " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > - "1:\n" > > - : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->coun= ter) > > - : [a]"r" (a), [u]"r" (u) > > - : "memory"); > > + _arch_atomic_fetch_add_unless(prev, rc, v->counter, a, u, "w"); > > + > > return prev; > > } > > #define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless > > @@ -222,17 +228,8 @@ static __always_inline s64 arch_atomic64_fetch_add= _unless(atomic64_t *v, s64 a, > > s64 prev; > > long rc; > > > > - __asm__ __volatile__ ( > > - "0: lr.d %[p], %[c]\n" > > - " beq %[p], %[u], 1f\n" > > - " add %[rc], %[p], %[a]\n" > > - " sc.d.rl %[rc], %[rc], %[c]\n" > > - " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > - "1:\n" > > - : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->coun= ter) > > - : [a]"r" (a), [u]"r" (u) > > - : "memory"); > > + _arch_atomic_fetch_add_unless(prev, rc, v->counter, a, u, "d"); > > + > > return prev; > > } > > #define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless > > @@ -310,61 +307,79 @@ ATOMIC_OPS() > > #undef ATOMIC_OPS > > #undef ATOMIC_OP > > > > +#define _arch_atomic_inc_unless_negative(_prev, _rc, counter, sfx) = \ > > +({ = \ > > + __asm__ __volatile__ ( = \ > > + "0: lr." sfx " %[p], %[c]\n" = \ > > + " bltz %[p], 1f\n" = \ > > + " addi %[rc], %[p], 1\n" = \ > > + " sc." sfx ".rl %[rc], %[rc], %[c]\n" = \ > > + " bnez %[rc], 0b\n" = \ > > + " fence rw, rw\n" = \ > > + "1:\n" = \ > > + : [p]"=3D&r" (_prev), [rc]"=3D&r" (_rc), [c]"+A" (count= er) \ > > + : = \ > > + : "memory"); = \ > > +}) > > + > > static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *= v) > > { > > int prev, rc; > > > > - __asm__ __volatile__ ( > > - "0: lr.w %[p], %[c]\n" > > - " bltz %[p], 1f\n" > > - " addi %[rc], %[p], 1\n" > > - " sc.w.rl %[rc], %[rc], %[c]\n" > > - " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > - "1:\n" > > - : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->coun= ter) > > - : > > - : "memory"); > > + _arch_atomic_inc_unless_negative(prev, rc, v->counter, "w"); > > + > > return !(prev < 0); > > } > > > > #define arch_atomic_inc_unless_negative arch_atomic_inc_unless_negativ= e > > > > +#define _arch_atomic_dec_unless_positive(_prev, _rc, counter, sfx) = \ > > +({ = \ > > + __asm__ __volatile__ ( = \ > > + "0: lr." sfx " %[p], %[c]\n" = \ > > + " bgtz %[p], 1f\n" = \ > > + " addi %[rc], %[p], -1\n" = \ > > + " sc." sfx ".rl %[rc], %[rc], %[c]\n" = \ > > + " bnez %[rc], 0b\n" = \ > > + " fence rw, rw\n" = \ > > + "1:\n" = \ > > + : [p]"=3D&r" (_prev), [rc]"=3D&r" (_rc), [c]"+A" (count= er) \ > > + : = \ > > + : "memory"); = \ > > +}) > > + > > static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *= v) > > { > > int prev, rc; > > > > - __asm__ __volatile__ ( > > - "0: lr.w %[p], %[c]\n" > > - " bgtz %[p], 1f\n" > > - " addi %[rc], %[p], -1\n" > > - " sc.w.rl %[rc], %[rc], %[c]\n" > > - " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > - "1:\n" > > - : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->coun= ter) > > - : > > - : "memory"); > > + _arch_atomic_dec_unless_positive(prev, rc, v->counter, "w"); > > + > > return !(prev > 0); > > } > > > > #define arch_atomic_dec_unless_positive arch_atomic_dec_unless_positiv= e > > > > +#define _arch_atomic_dec_if_positive(_prev, _rc, counter, sfx) = \ > > +({ = \ > > + __asm__ __volatile__ ( = \ > > + "0: lr." sfx " %[p], %[c]\n" = \ > > + " addi %[rc], %[p], -1\n" = \ > > + " bltz %[rc], 1f\n" = \ > > + " sc." sfx ".rl %[rc], %[rc], %[c]\n" = \ > > + " bnez %[rc], 0b\n" = \ > > + " fence rw, rw\n" = \ > > + "1:\n" = \ > > + : [p]"=3D&r" (_prev), [rc]"=3D&r" (_rc), [c]"+A" (count= er) \ > > + : = \ > > + : "memory"); = \ > > +}) > > + > > static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) > > { > > int prev, rc; > > > > - __asm__ __volatile__ ( > > - "0: lr.w %[p], %[c]\n" > > - " addi %[rc], %[p], -1\n" > > - " bltz %[rc], 1f\n" > > - " sc.w.rl %[rc], %[rc], %[c]\n" > > - " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > - "1:\n" > > - : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->coun= ter) > > - : > > - : "memory"); > > + _arch_atomic_dec_if_positive(prev, rc, v->counter, "w"); > > + > > return prev - 1; > > } > > > > @@ -376,17 +391,8 @@ static __always_inline bool arch_atomic64_inc_unle= ss_negative(atomic64_t *v) > > s64 prev; > > long rc; > > > > - __asm__ __volatile__ ( > > - "0: lr.d %[p], %[c]\n" > > - " bltz %[p], 1f\n" > > - " addi %[rc], %[p], 1\n" > > - " sc.d.rl %[rc], %[rc], %[c]\n" > > - " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > - "1:\n" > > - : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->coun= ter) > > - : > > - : "memory"); > > + _arch_atomic_inc_unless_negative(prev, rc, v->counter, "d"); > > + > > return !(prev < 0); > > } > > > > @@ -397,17 +403,8 @@ static __always_inline bool arch_atomic64_dec_unle= ss_positive(atomic64_t *v) > > s64 prev; > > long rc; > > > > - __asm__ __volatile__ ( > > - "0: lr.d %[p], %[c]\n" > > - " bgtz %[p], 1f\n" > > - " addi %[rc], %[p], -1\n" > > - " sc.d.rl %[rc], %[rc], %[c]\n" > > - " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > - "1:\n" > > - : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->coun= ter) > > - : > > - : "memory"); > > + _arch_atomic_dec_unless_positive(prev, rc, v->counter, "d"); > > + > > return !(prev > 0); > > } > > > > @@ -418,17 +415,8 @@ static __always_inline s64 arch_atomic64_dec_if_po= sitive(atomic64_t *v) > > s64 prev; > > long rc; > > > > - __asm__ __volatile__ ( > > - "0: lr.d %[p], %[c]\n" > > - " addi %[rc], %[p], -1\n" > > - " bltz %[rc], 1f\n" > > - " sc.d.rl %[rc], %[rc], %[c]\n" > > - " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > - "1:\n" > > - : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->coun= ter) > > - : > > - : "memory"); > > + _arch_atomic_dec_if_positive(prev, rc, v->counter, "d"); > > + > > return prev - 1; > > } > > > > -- > > 2.40.0 > > > A safe cleanup, no problem found. Reviewed-by: Guo Ren --=20 Best Regards Guo Ren