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References: <20230517-topic-a7xx_prep-v2-0-5b9daa2b2cf0@linaro.org> <20230517-topic-a7xx_prep-v2-2-5b9daa2b2cf0@linaro.org>
In-Reply-To: <20230517-topic-a7xx_prep-v2-2-5b9daa2b2cf0@linaro.org>
From:   Rob Clark <robdclark@gmail.com>
Date:   Thu, 25 May 2023 10:38:59 -0700
Message-ID: <CAF6AEGsm=o-KgOtm01FSvMOB_uj6VOaONNu5FUr4phUixYNG3g@mail.gmail.com>
Subject: Re: [PATCH v2 2/6] drm/msm/a6xx: Explain CP_PROTECT_CNTL writes in a6xx_set_cp_protect
To:     Konrad Dybcio <konrad.dybcio@linaro.org>
Cc:     Abhinav Kumar <quic_abhinavk@quicinc.com>,
        Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Marijn Suijten <marijn.suijten@somainline.org>,
        Jonathan Marek <jonathan@marek.ca>,
        linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
        freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
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On Fri, May 19, 2023 at 6:29=E2=80=AFAM Konrad Dybcio <konrad.dybcio@linaro=
.org> wrote:
>
> We have the necessary information, so explain which bit does what.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/=
adreno/a6xx_gpu.c
> index 9fb214f150dd..deed42675fe2 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -771,9 +771,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
>         }
>
>         /*
> -        * Enable access protection to privileged registers, fault on an =
access
> -        * protect violation and select the last span to protect from the=
 start
> -        * address all the way to the end of the register address space
> +        * BIT(0) - Enable access protection to privileged registers
> +        * BIT(1) - Enable fault on an access protect violation
> +        * BIT(3) - Select the last span to protect from the start
> +        *          address all the way to the end of the register addres=
s space

Even better would be to give these bitfields names in the xml, which
also gets you more meaningful decoding.  We've been better about not
open-coding a lot of stuff on the mesa side, but it is a bit easier
with header generation integrated into the build..  but less
open-coding on the kernel side is still a noble goal

BR,
-R

>          */
>         gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)=
);
>
>
> --
> 2.40.1
>