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Date:   Thu, 25 May 2023 22:36:38 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Minda Chen <minda.chen@starfivetech.com>
Cc:     Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        Vinod Koul <vkoul@kernel.org>,
        Kishon Vijay Abraham I <kishon@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Pawel Laszczak <pawell@cadence.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Peter Chen <peter.chen@kernel.org>,
        Roger Quadros <rogerq@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-phy@lists.infradead.org, linux-usb@vger.kernel.org,
        linux-riscv@lists.infradead.org,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Mason Huo <mason.huo@starfivetech.com>
Subject: Re: [PATCH v6 7/7] riscv: dts: starfive: Add USB dts configuration
 for JH7110
Message-ID: <20230525-cross-daybreak-24dfed69e5d0@spud>
References: <20230518112750.57924-1-minda.chen@starfivetech.com>
 <20230518112750.57924-8-minda.chen@starfivetech.com>
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Greg,

On Thu, May 18, 2023 at 07:27:50PM +0800, Minda Chen wrote:
> Add USB wrapper layer and Cadence USB3 controller dts
> configuration for StarFive JH7110 SoC and VisionFive2
> Board.
> USB controller connect to PHY, The PHY dts configuration
> are also added.
>=20
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>

> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/d=
ts/starfive/jh7110.dtsi
> index 71a8e9acbe55..b65f06c5b1b7 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -366,6 +366,59 @@
>  			status =3D "disabled";
>  		};
> =20
> +		usb0: usb@10100000 {
> +			compatible =3D "starfive,jh7110-usb";
> +			ranges =3D <0x0 0x0 0x10100000 0x100000>;
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			starfive,stg-syscon =3D <&stg_syscon 0x4>;
> +			clocks =3D <&stgcrg JH7110_STGCLK_USB0_LPM>,

Please don't pick this patch, if the rest of the series is applicable,
as this will break building the dtb as stgcrg does not yet exist in any
maintainer tree.

Thanks,
Conor.

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