Received: by 2002:a05:6358:3188:b0:123:57c1:9b43 with SMTP id q8csp2820161rwd; Fri, 26 May 2023 11:43:40 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ74ds85/vTGfEbfchWll2JCB2P0Gic4QJxZR59Hxex/fGlUzIA4kSNEoLPGNxGPHqnMNjxz X-Received: by 2002:a17:90a:7648:b0:253:9766:749e with SMTP id s8-20020a17090a764800b002539766749emr3268756pjl.16.1685126620170; Fri, 26 May 2023 11:43:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685126620; cv=none; d=google.com; s=arc-20160816; b=R3F7UYfOOt81jzlQwHlGHdzjWLX1sEtGXTP/1N01o8OmNasgJpsbyIU+R7MNpItvZp UloSzh5cMawticuurs/p8znBUWv+dTbKke5tHpseyGRCqbtLqZNI22e0QK32enxdNVwX c17XIZGT5bJou0GlpefkErJVZP9XW552SsHqtya6C99ibdxSwprqG2xFwC1OzbaxepBF tZFNX5t1JSSP9SJ2X+UNHQBgYJSMyZ7/p052WdsEheoe/MYV+V/p8PvlP1qrDI1oJOgt /p0uBEbdRSeyXOk7/GDm5whRIBgRuDZAmfxF1Y4831yFofsv1PeD1DIFQVoN0doT5pv+ +zOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:to:content-language:subject:user-agent:mime-version:date :message-id:dkim-signature; bh=vlJmRe7qm4TXdgUWvggV7PZRS4mr0NGri/EDHhZqjUs=; b=OZKgifJGSDqjf18garwZaOUpC4GF3zYDeprCmDjBb5lnWhTD/wpyZsvMvKAhuEObMC wVvW63wYri6CUtSDPBXn37iA0fVYcOgQMVOztPNJxwxMn0L5Z5NKEwsRj8egWPEScEMl uY7qk+8NsN+eNVi8n8jj3f1QOnznAszB91Q5xVImMRElUS+odkRb0OjICEWP54tWGoB3 LdXqcRmBDNUFixs1qhRiRFVcuPVjQw+KKBLSSyl8NZYf18voZj15Trpy5I+Rt/CSCbcf VhGS26YQkbEY8z56SuQ/3fD3r5unnssmkoVaPZdsNBzDObLKOlBsiOkwgcu1rPRLGtJ/ sVWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gbo5vNyw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x9-20020a17090a970900b0025620801ed4si2659454pjo.1.2023.05.26.11.43.26; Fri, 26 May 2023 11:43:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gbo5vNyw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230376AbjEZSRT (ORCPT + 99 others); Fri, 26 May 2023 14:17:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230121AbjEZSRR (ORCPT ); Fri, 26 May 2023 14:17:17 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BEB412A; Fri, 26 May 2023 11:17:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685125032; x=1716661032; h=message-id:date:mime-version:subject:to:references:from: in-reply-to:content-transfer-encoding; bh=o3P5GMOHUbd1RynT+xVq4dnw3tawyMZSbeXlFyQDd1A=; b=gbo5vNywOta5U3Bs9JQzwOXT2iy/h/g/29nVGUCnXCFjBwEZuonFCUOx 2QxMrDNgzWcb6B1WIKGgI+QOuV1WNYmQGD6nIoUL/qsgtSLuFgBIvJaa2 BxL0o+xcm8yDmCJba+iUc+46JLQScXsTztVMFSYa0iQtYEAERPUI0qFAD 3gHo0nJ62IKyFV3nqhfxjCTKAG4OOslPDFzWidMx4BAWoeriWqp5oQaZT o8UE1VsOx0vEs/D7mePviJZosJIr5ogQOZQPhLPA9HzrGRCHV0HsKVOzg 1pLslJ+WbI3pYOQg+bHUBDayZQtkd5kZQOhul8pVfNSnY/wye1PhTaYOS A==; X-IronPort-AV: E=McAfee;i="6600,9927,10722"; a="353113061" X-IronPort-AV: E=Sophos;i="6.00,194,1681196400"; d="scan'208";a="353113061" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2023 11:17:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10722"; a="795170762" X-IronPort-AV: E=Sophos;i="6.00,194,1681196400"; d="scan'208";a="795170762" Received: from linux.intel.com ([10.54.29.200]) by FMSMGA003.fm.intel.com with ESMTP; 26 May 2023 11:17:09 -0700 Received: from [10.209.100.85] (kliang2-mobl1.ccr.corp.intel.com [10.209.100.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by linux.intel.com (Postfix) with ESMTPS id C6AC95807E2; Fri, 26 May 2023 11:17:05 -0700 (PDT) Message-ID: Date: Fri, 26 May 2023 14:17:04 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.1 Subject: Re: [PATCH v3 00/35] PMU refactoring and improvements Content-Language: en-US To: Ian Rogers , Suzuki K Poulose , Mike Leach , Leo Yan , John Garry , Will Deacon , James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Kajol Jain , Jing Zhang , Ravi Bangoria , Madhavan Srinivasan , Athira Rajeev , Ming Wang , Huacai Chen , Sandipan Das , Dmitrii Dolgov <9erthalion6@gmail.com>, Sean Christopherson , Ali Saidi , Rob Herring , Thomas Richter , Kang Minchul , linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org References: <20230524221831.1741381-1-irogers@google.com> From: "Liang, Kan" In-Reply-To: <20230524221831.1741381-1-irogers@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023-05-24 6:17 p.m., Ian Rogers wrote: > Separate the code in pmu.[ch] into the set/list of PMUs and the code > for a particular PMU. Move the set/list of PMUs code into > pmus.[ch]. Clean up hybrid code and remove hybrid PMU list, it is > sufficient to scan PMUs looking for core ones. Add core PMU list and > perf_pmus__scan_core that just reads core PMUs. Switch code that skips > non-core PMUs during a perf_pmus__scan, to use the > perf_pmus__scan_core variant. Don't scan sysfs for PMUs if all such > PMUs have been previously scanned/loaded. Scanning just core PMUs, for > the cases it is applicable, can improve the sysfs reading time by more > than 4 fold on my laptop, as servers generally have many more uncore > PMUs the improvement there should be larger: > > ``` > $ perf bench internals pmu-scan -i 1000 > Computing performance of sysfs PMU event scan for 1000 times > Average core PMU scanning took: 989.231 usec (+- 1.535 usec) > Average PMU scanning took: 4309.425 usec (+- 74.322 usec) > ``` > > The patch "perf pmu: Separate pmu and pmus" moves and renames a lot of > functions, and is consequently large. The changes are trivial, but > kept together to keep the overall number of patches more reasonable. > Other than the small suggestion in patch 16, the patch set looks good to me. Thanks Ian! Reviewed-by: Kan Liang Thanks, Kan > v3. Address fixing hybrid user specified CPU maps by doing it in > propagate maps. Remove nearly all references to cpu_core/cpu_atom > in particular by removing is_pmu_hybrid - hybrid is now >1 core > PMU. Addresses comments by Kan and Namhyung. > v2. Address Kan's review comments wrt "cycles" -> "cycles:P" and > "uncore_pmus" -> "other_pmus". > > Ian Rogers (35): > perf cpumap: Add intersect function > perf tests: Organize cpu_map tests into a single suite > perf cpumap: Add equal function > libperf cpumap: Add "any CPU"/dummy test function > perf pmu: Detect ARM and hybrid PMUs with sysfs > perf pmu: Add is_core to pmu > perf evsel: Add is_pmu_core inorder to interpret own_cpus > perf pmu: Add CPU map for "cpu" PMUs > perf evlist: Propagate user CPU maps intersecting core PMU maps > perf evlist: Allow has_user_cpus to be set on hybrid > perf target: Remove unused hybrid value > perf tools: Warn if no user requested CPUs match PMU's CPUs > perf evlist: Remove evlist__warn_hybrid_group > perf evlist: Remove __evlist__add_default > perf evlist: Reduce scope of evlist__has_hybrid > perf pmu: Remove perf_pmu__hybrid_mounted > perf pmu: Rewrite perf_pmu__has_hybrid to avoid list > perf x86: Iterate hybrid PMUs as core PMUs > perf topology: Avoid hybrid list for hybrid topology > perf evsel: Compute is_hybrid from PMU being core > perf header: Avoid hybrid PMU list in write_pmu_caps > perf metrics: Remove perf_pmu__is_hybrid use > perf stat: Avoid hybrid PMU list > perf mem: Avoid hybrid PMU list > perf pmu: Remove perf_pmu__hybrid_pmus list > perf pmus: Prefer perf_pmu__scan over perf_pmus__for_each_pmu > perf x86 mem: minor refactor to is_mem_loads_aux_event > perf pmu: Separate pmu and pmus > perf pmus: Split pmus list into core and other > perf pmus: Allow just core PMU scanning > perf pmus: Avoid repeated sysfs scanning > perf pmus: Ensure all PMUs are read for find_by_type > perf pmus: Add function to return count of core PMUs > perf pmus: Remove perf_pmus__has_hybrid > perf pmu: Remove is_pmu_hybrid > > tools/lib/perf/cpumap.c | 61 +++ > tools/lib/perf/evlist.c | 25 +- > tools/lib/perf/include/internal/evsel.h | 9 + > tools/lib/perf/include/perf/cpumap.h | 14 + > tools/perf/arch/arm/util/auxtrace.c | 7 +- > tools/perf/arch/arm/util/cs-etm.c | 4 +- > tools/perf/arch/arm64/util/pmu.c | 6 +- > tools/perf/arch/x86/tests/hybrid.c | 7 +- > tools/perf/arch/x86/util/auxtrace.c | 5 +- > tools/perf/arch/x86/util/evlist.c | 25 +- > tools/perf/arch/x86/util/evsel.c | 27 +- > tools/perf/arch/x86/util/intel-bts.c | 4 +- > tools/perf/arch/x86/util/intel-pt.c | 4 +- > tools/perf/arch/x86/util/mem-events.c | 17 +- > tools/perf/arch/x86/util/perf_regs.c | 15 +- > tools/perf/arch/x86/util/topdown.c | 5 +- > tools/perf/bench/pmu-scan.c | 60 +-- > tools/perf/builtin-c2c.c | 9 +- > tools/perf/builtin-list.c | 4 +- > tools/perf/builtin-mem.c | 9 +- > tools/perf/builtin-record.c | 29 +- > tools/perf/builtin-stat.c | 14 +- > tools/perf/builtin-top.c | 10 +- > tools/perf/tests/attr.c | 11 +- > tools/perf/tests/builtin-test.c | 4 +- > tools/perf/tests/cpumap.c | 92 ++++- > tools/perf/tests/event_groups.c | 7 +- > tools/perf/tests/parse-events.c | 15 +- > tools/perf/tests/parse-metric.c | 9 +- > tools/perf/tests/pmu-events.c | 6 +- > tools/perf/tests/switch-tracking.c | 14 +- > tools/perf/tests/tests.h | 4 +- > tools/perf/tests/topology.c | 16 +- > tools/perf/util/Build | 2 - > tools/perf/util/cpumap.c | 4 +- > tools/perf/util/cpumap.h | 4 +- > tools/perf/util/cputopo.c | 12 +- > tools/perf/util/env.c | 5 +- > tools/perf/util/evlist-hybrid.c | 162 -------- > tools/perf/util/evlist-hybrid.h | 15 - > tools/perf/util/evlist.c | 64 +++- > tools/perf/util/evlist.h | 9 +- > tools/perf/util/evsel.c | 60 +-- > tools/perf/util/evsel.h | 3 - > tools/perf/util/header.c | 27 +- > tools/perf/util/mem-events.c | 25 +- > tools/perf/util/metricgroup.c | 9 +- > tools/perf/util/parse-events.c | 25 +- > tools/perf/util/parse-events.y | 3 +- > tools/perf/util/pfm.c | 6 +- > tools/perf/util/pmu-hybrid.c | 52 --- > tools/perf/util/pmu-hybrid.h | 32 -- > tools/perf/util/pmu.c | 483 ++---------------------- > tools/perf/util/pmu.h | 25 +- > tools/perf/util/pmus.c | 465 ++++++++++++++++++++++- > tools/perf/util/pmus.h | 15 +- > tools/perf/util/print-events.c | 15 +- > tools/perf/util/python-ext-sources | 1 - > tools/perf/util/stat-display.c | 19 +- > tools/perf/util/target.h | 1 - > 60 files changed, 1002 insertions(+), 1089 deletions(-) > delete mode 100644 tools/perf/util/evlist-hybrid.c > delete mode 100644 tools/perf/util/evlist-hybrid.h > delete mode 100644 tools/perf/util/pmu-hybrid.c > delete mode 100644 tools/perf/util/pmu-hybrid.h >