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From:   Haibo Xu <xiaobo55x@gmail.com>
Date:   Sat, 27 May 2023 10:26:51 +0800
Message-ID: <CAJve8on=5NtnzR=iAQs2D4B2Ly=KFXF-0ZDtkXFuz-SdxTGGmA@mail.gmail.com>
Subject: Re: [PATCH v2 09/11] KVM: riscv: selftests: Make check_supported arch specific
To:     Andrew Jones <ajones@ventanamicro.com>
Cc:     Haibo Xu <haibo1.xu@intel.com>, maz@kernel.org,
        oliver.upton@linux.dev, seanjc@google.com,
        Paolo Bonzini <pbonzini@redhat.com>,
        Jonathan Corbet <corbet@lwn.net>,
        Anup Patel <anup@brainfault.org>,
        Atish Patra <atishp@atishpatra.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Shuah Khan <shuah@kernel.org>,
        James Morse <james.morse@arm.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Zenghui Yu <yuzenghui@huawei.com>,
        David Matlack <dmatlack@google.com>,
        Ben Gardon <bgardon@google.com>,
        Vipin Sharma <vipinsh@google.com>,
        Colton Lewis <coltonlewis@google.com>, kvm@vger.kernel.org,
        linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
        kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
        linux-kselftest@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
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On Fri, May 26, 2023 at 4:44=E2=80=AFPM Andrew Jones <ajones@ventanamicro.c=
om> wrote:
>
> On Fri, May 26, 2023 at 03:50:32PM +0800, Haibo Xu wrote:
> > On Fri, May 26, 2023 at 12:40=E2=80=AFAM Andrew Jones <ajones@ventanami=
cro.com> wrote:
> > >
> > > On Thu, May 25, 2023 at 03:38:33PM +0800, Haibo Xu wrote:
> > > > check_supported() was used to verify whether a feature/extension wa=
s
> > > > supported in a guest in the get-reg-list test. Currently this info
> > > > can be retrieved through the KVM_CAP_ARM_* API in aarch64, but in
> > > > riscv, this info was only exposed through the KVM_GET_ONE_REG on
> > > > KVM_REG_RISCV_ISA_EXT pseudo registers.
> > > >
> > > > Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
> > > > ---
> > > >  tools/testing/selftests/kvm/get-reg-list.c | 32 +++++++++++-------=
----
> > > >  1 file changed, 16 insertions(+), 16 deletions(-)
> > > >
> > > > diff --git a/tools/testing/selftests/kvm/get-reg-list.c b/tools/tes=
ting/selftests/kvm/get-reg-list.c
> > > > index f6ad7991a812..f1fc113e9719 100644
> > > > --- a/tools/testing/selftests/kvm/get-reg-list.c
> > > > +++ b/tools/testing/selftests/kvm/get-reg-list.c
> > > > @@ -99,6 +99,20 @@ void __weak print_reg(const char *prefix, __u64 =
id)
> > > >  }
> > > >
> > > >  #ifdef __aarch64__
> > > > +static void check_supported(struct vcpu_reg_list *c)
> > > > +{
> > > > +     struct vcpu_reg_sublist *s;
> > > > +
> > > > +     for_each_sublist(c, s) {
> > > > +             if (!s->capability)
> > > > +                     continue;
> > >
> > > I was going to say that making this function aarch64 shouldn't be
> > > necessary, since riscv leaves capability set to zero and this functio=
n
> > > doesn't do anything, but then looking ahead I see riscv is abusing
> > > capability by putting isa extensions in it. IMO, capability should
> > > only be set to KVM_CAP_* values. Since riscv doesn't use it, then it
> > > should be left zero.
> > >
> > > If we're going to abuse something, then I'd rather abuse the 'feature=
'
> > > member, but since it's only an int (not an unsigned long), then let's
> > > just add an 'unsigned long extension' member.
> > >
> >
> > Good idea!
> >
> > For the new 'extension' member in riscv, I think its use case should be
> > identical to the 'feature' member in aarch64(KVM_RISCV_ISA_EXT_F
> > was similar to KVM_ARM_VCPU_SVE)? If so, I think we can just reuse
> > the 'feature' member since the data type was not a big deal.
>
> You're right. An int is fine for the isa extension index, which is all we
> need to represent.
>
> Thanks,
> drew

Thanks for the suggestion! I will include the change in v3 soon.