Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Thomas Gleixner <tglx@linutronix.de>
To:     Linus Torvalds <torvalds@linux-foundation.org>
Cc:     linux-kernel@vger.kernel.org, x86@kernel.org
Subject: [GIT pull] perf/urgent for 6.4-rc4
References: <168526035526.3457722.14103350194452732675.tglx@xen13>
Message-ID: <168526035979.3457722.10299010241065106864.tglx@xen13>
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
Date:   Sun, 28 May 2023 09:53:00 +0200 (CEST)
Precedence: bulk

Linus,

please pull the latest perf/urgent branch from:

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-urgent-2023=
-05-28

up to:  38776cc45eb7: perf/x86/uncore: Correct the number of CHAs on SPR


A small set of perf fixes:

 - Make the CHA discovery based on MSR readout to work around broken
   discovery tables in some SPR firmwares.

 - Prevent saving PEBS configuration which has software bits set that
   cause a crash when restored into the relevant MSR.

Thanks,

	tglx

------------------>
Kan Liang (1):
      perf/x86/uncore: Correct the number of CHAs on SPR

Like Xu (1):
      perf/x86/intel: Save/restore cpuc->active_pebs_data_cfg when using gues=
t PEBS


 arch/x86/events/intel/core.c         |  2 +-
 arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 070cc4ef2672..89b9c1cebb61 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4074,7 +4074,7 @@ static struct perf_guest_switch_msr *intel_guest_get_ms=
rs(int *nr, void *data)
 	if (x86_pmu.intel_cap.pebs_baseline) {
 		arr[(*nr)++] =3D (struct perf_guest_switch_msr){
 			.msr =3D MSR_PEBS_DATA_CFG,
-			.host =3D cpuc->pebs_data_cfg,
+			.host =3D cpuc->active_pebs_data_cfg,
 			.guest =3D kvm_pmu->pebs_data_cfg,
 		};
 	}
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/unc=
ore_snbep.c
index fa9b209a11fa..d49e90dc04a4 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -6150,6 +6150,7 @@ static struct intel_uncore_type spr_uncore_mdf =3D {
 };
=20
 #define UNCORE_SPR_NUM_UNCORE_TYPES		12
+#define UNCORE_SPR_CHA				0
 #define UNCORE_SPR_IIO				1
 #define UNCORE_SPR_IMC				6
 #define UNCORE_SPR_UPI				8
@@ -6460,12 +6461,22 @@ static int uncore_type_max_boxes(struct intel_uncore_=
type **types,
 	return max + 1;
 }
=20
+#define SPR_MSR_UNC_CBO_CONFIG		0x2FFE
+
 void spr_uncore_cpu_init(void)
 {
+	struct intel_uncore_type *type;
+	u64 num_cbo;
+
 	uncore_msr_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MSR,
 						UNCORE_SPR_MSR_EXTRA_UNCORES,
 						spr_msr_uncores);
=20
+	type =3D uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
+	if (type) {
+		rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
+		type->num_boxes =3D num_cbo;
+	}
 	spr_uncore_iio_free_running.num_boxes =3D uncore_type_max_boxes(uncore_msr_=
uncores, UNCORE_SPR_IIO);
 }
=20