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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i68-20020a625447000000b0064d421691a6si3370498pfb.245.2023.05.29.01.54.08; Mon, 29 May 2023 01:54:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=eDjZXxBr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231600AbjE2Iqs (ORCPT + 99 others); Mon, 29 May 2023 04:46:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231612AbjE2Iqn (ORCPT ); Mon, 29 May 2023 04:46:43 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B818102; Mon, 29 May 2023 01:46:33 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 080C6612FB; Mon, 29 May 2023 08:46:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B7D3C4339B; Mon, 29 May 2023 08:46:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685349992; bh=jf544nMnrrkzn5ADVC/f/s+6Ap+dr5yU1BPKr7SBhq4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eDjZXxBrOIUdx5H1DZTFEzfLDMa1t+veVdiUgBDWwZqMjzcdlM6Ek5DC0G0nNdl8f ImhvVBzWx96T6OQWkxfzvp/geEkhoMtDCk22mvh0dN6FDDqNvN8GJBIdYdL/qFVLJq 393Y+zXnIvccrtKjACGF45lrJMQMSM4mtU0oNrCwebKX+UikJ5I6VRLnqAZnXLhpgW sWARuJJg8x4JUHgo+5FJyiOeP5K03W+rGilBRq5BpharrxABq4lgfj8GL3b45f7t04 K1+TBOKtVmyWkMKD5AiJ6rHU9f5mmeFV6v8uLUPztEnUJjg7dwdNX26pHycO3Gq/xy ExopRPRK10RPg== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, bjorn@kernel.org, greentime.hu@sifive.com, vincent.chen@sifive.com, andy.chiu@sifive.com, paul.walmsley@sifive.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH -next V12 2/3] riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK Date: Mon, 29 May 2023 04:45:59 -0400 Message-Id: <20230529084600.2878130-3-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230529084600.2878130-1-guoren@kernel.org> References: <20230529084600.2878130-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren Add the HAVE_SOFTIRQ_ON_OWN_STACK feature for the IRQ_STACKS config, and the irq and softirq use the same irq_stack of percpu. Tested-by: Jisheng Zhang Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 6 ++++-- arch/riscv/kernel/irq.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 44b4c9690f94..9567bf5fd5ed 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -589,11 +589,13 @@ config FPU If you don't know what to do here, say Y. config IRQ_STACKS - bool "Independent irq stacks" if EXPERT + bool "Independent irq & softirq stacks" if EXPERT default y select HAVE_IRQ_EXIT_ON_IRQ_STACK + select HAVE_SOFTIRQ_ON_OWN_STACK help - Add independent irq stacks for percpu to prevent kernel stack overflows. + Add independent irq & softirq stacks for percpu to prevent kernel stack + overflows. We may save some memory footprint by disabling IRQ_STACKS. endmenu # "Platform type" diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index a1dcf8e43b3c..d0577cc6a081 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -11,6 +11,9 @@ #include #include #include +#include +#include +#include static struct fwnode_handle *(*__get_intc_node)(void); @@ -56,6 +59,38 @@ static void init_irq_stacks(void) per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu); } #endif /* CONFIG_VMAP_STACK */ + +#ifdef CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK +void do_softirq_own_stack(void) +{ +#ifdef CONFIG_IRQ_STACKS + if (on_thread_stack()) { + ulong *sp = per_cpu(irq_stack_ptr, smp_processor_id()) + + IRQ_STACK_SIZE/sizeof(ulong); + __asm__ __volatile( + "addi sp, sp, -"RISCV_SZPTR "\n" + REG_S" ra, (sp) \n" + "addi sp, sp, -"RISCV_SZPTR "\n" + REG_S" s0, (sp) \n" + "addi s0, sp, 2*"RISCV_SZPTR "\n" + "move sp, %[sp] \n" + "call __do_softirq \n" + "addi sp, s0, -2*"RISCV_SZPTR"\n" + REG_L" s0, (sp) \n" + "addi sp, sp, "RISCV_SZPTR "\n" + REG_L" ra, (sp) \n" + "addi sp, sp, "RISCV_SZPTR "\n" + : + : [sp] "r" (sp) + : "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "memory"); + } else +#endif + __do_softirq(); +} +#endif /* CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK */ + #else static void init_irq_stacks(void) {} #endif /* CONFIG_IRQ_STACKS */ -- 2.36.1