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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id m25-20020a2e97d9000000b002a8b9570403sm2346883ljj.31.2023.05.29.01.47.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 May 2023 01:47:17 -0700 (PDT) Message-ID: <254cd131-4ad1-44c9-2653-862580503c15@linaro.org> Date: Mon, 29 May 2023 11:47:17 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 0/5] MDSS reg bus interconnect Content-Language: en-GB To: Konrad Dybcio Cc: Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230417-topic-dpu_regbus-v1-0-06fbdc1643c0@linaro.org> <74a817ff-5850-330d-8cac-f551be6fa35c@linaro.org> From: Dmitry Baryshkov In-Reply-To: <74a817ff-5850-330d-8cac-f551be6fa35c@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/05/2023 10:42, Konrad Dybcio wrote: > > > On 29.05.2023 04:42, Dmitry Baryshkov wrote: >> On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote: >>> >>> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's >>> another path that needs to be handled to ensure MDSS functions properly, >>> namely the "reg bus", a.k.a the CPU-MDSS interconnect. >>> >>> Gating that path may have a variety of effects.. from none to otherwise >>> inexplicable DSI timeouts.. >>> >>> This series tries to address the lack of that. >>> >>> Example path: >>> >>> interconnects = <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_DISPLAY_CFG 0>; >> >> If we are going to touch the MDSS interconnects, could you please also >> add the rotator interconnect to the bindings? >> We do not need to touch it at this time, but let's not have to change >> bindings later again. >> > Ack Also, several points noted from the mdss fbdev driver: - All possible clents vote for the low bw setting. This includes DSI, HDMI, MDSS itself and INTF - SMMU also casts such vote, which I do not think should be necessary, unless there is a separate MDSS SMMU? - PINGPONG cacsts high bw setting for the sake of speeding up the LUT tables if required. -- With best wishes Dmitry